diff options
| author | Nico Huber <nico.h@gmx.de> | 2019-05-04 16:59:20 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-07 15:55:50 +0000 |
| commit | 66318aad07e6810065bc0668f4a1f34b7cb77687 (patch) | |
| tree | 6b55edcdc8f54bf0d0f65365cd7ee0ccb5fe2884 /src/drivers/intel/fsp1_1/romstage.c | |
| parent | 99e836c843e6a8536348d5cc9581b5a17512a263 (diff) | |
intel/fsp1_1: Move MRC cache pointers into `romstage_params`
These are part of a common concept and not SoC specific.
Change-Id: I9cb218d7825bd06a138f7f5d9e2b68e86077a3ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1/romstage.c')
| -rw-r--r-- | src/drivers/intel/fsp1_1/romstage.c | 25 |
1 files changed, 11 insertions, 14 deletions
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 17bd638290..87fd1a4c01 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -94,13 +94,11 @@ void romstage_common(struct romstage_params *params) { bool s3wake; struct region_device rdev; - struct pei_data *pei_data; post_code(0x32); timestamp_add_now(TS_BEFORE_INITRAM); - pei_data = params->pei_data; s3wake = params->power_state->prev_sleep_state == ACPI_S3; if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) @@ -111,9 +109,9 @@ void romstage_common(struct romstage_params *params) post_code(0x33); /* Check recovery and MRC cache */ - params->pei_data->saved_data_size = 0; - params->pei_data->saved_data = NULL; - if (!params->pei_data->disable_saved_data) { + params->saved_data_size = 0; + params->saved_data = NULL; + if (!params->disable_saved_data) { if (vboot_recovery_mode_enabled()) { /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, @@ -123,9 +121,8 @@ void romstage_common(struct romstage_params *params) params->fsp_version, &rdev))) { /* MRC cache found */ - params->pei_data->saved_data_size = - region_device_sz(&rdev); - params->pei_data->saved_data = rdev_mmap_full(&rdev); + params->saved_data_size = region_device_sz(&rdev); + params->saved_data = rdev_mmap_full(&rdev); /* Assume boot device is memory mapped. */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); } else if (s3wake) { @@ -146,15 +143,15 @@ void romstage_common(struct romstage_params *params) /* Save MRC output */ if (CONFIG(CACHE_MRC_SETTINGS)) { - printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", - pei_data->data_to_save, pei_data->data_to_save_size); + printk(BIOS_DEBUG, "MRC data at %p %zu bytes\n", + params->data_to_save, params->data_to_save_size); if (!s3wake - && (params->pei_data->data_to_save_size != 0) - && (params->pei_data->data_to_save != NULL)) + && (params->data_to_save_size != 0) + && (params->data_to_save != NULL)) mrc_cache_stash_data(MRC_TRAINING_DATA, params->fsp_version, - params->pei_data->data_to_save, - params->pei_data->data_to_save_size); + params->data_to_save, + params->data_to_save_size); } /* Save DIMM information */ |