diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/drivers/intel/fsp1_0 | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/drivers/intel/fsp1_0')
| -rw-r--r-- | src/drivers/intel/fsp1_0/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_0/fastboot_cache.c | 2 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_0/fsp_util.c | 10 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_0/fsp_util.h | 4 |
4 files changed, 9 insertions, 9 deletions
diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc index 8ac3595867..7897dd4003 100644 --- a/src/drivers/intel/fsp1_0/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc @@ -95,7 +95,7 @@ before_romstage: jmp .Lhlt .Lhlt: -#if IS_ENABLED(CONFIG_POST_IO) +#if CONFIG(POST_IO) outb %al, $CONFIG_POST_IO_PORT #endif hlt diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c index 76241c8f90..088c292e8d 100644 --- a/src/drivers/intel/fsp1_0/fastboot_cache.c +++ b/src/drivers/intel/fsp1_0/fastboot_cache.c @@ -57,7 +57,7 @@ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { size_t region_size; - if (IS_ENABLED(CONFIG_MRC_CACHE_FMAP)) { + if (CONFIG(MRC_CACHE_FMAP)) { struct region_device rdev; if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) { *mrc_region_ptr = rdev_mmap_full(&rdev); diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index 71f64161cc..2da07d519b 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -72,19 +72,19 @@ void __noreturn fsp_early_init (FSP_INFO_HEADER *fsp_ptr) FSP_FSP_INIT FspInitApi; FSP_INIT_PARAMS FspInitParams; FSP_INIT_RT_BUFFER FspRtBuffer; -#if IS_ENABLED(CONFIG_FSP_USES_UPD) +#if CONFIG(FSP_USES_UPD) UPD_DATA_REGION fsp_upd_data; #endif /* Load microcode before RAM init */ - if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS)) + if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) intel_update_microcode_from_cbfs(); memset((void *)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER)); FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP; FspInitParams.NvsBufferPtr = NULL; -#if IS_ENABLED(CONFIG_FSP_USES_UPD) +#if CONFIG(FSP_USES_UPD) FspRtBuffer.Common.UpdDataRgnPtr = &fsp_upd_data; #endif FspInitParams.RtBufferPtr = (FSP_INIT_RT_BUFFER *)&FspRtBuffer; @@ -238,7 +238,7 @@ void print_fsp_info(void) { } -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) +#if CONFIG(ENABLE_MRC_CACHE) /** * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM */ @@ -308,7 +308,7 @@ static void find_fsp_hob_update_mrc(void *unused) /* 0x0000: Print all types */ print_hob_type_structure(0x000, FspHobListPtr); - #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) + #if CONFIG(ENABLE_MRC_CACHE) if (save_mrc_data(FspHobListPtr)) update_mrc_cache(NULL); else diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index d5d0160e49..f781329d21 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -19,7 +19,7 @@ #include <chipset_fsp_util.h> #include "fsp_values.h" -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) +#if CONFIG(ENABLE_MRC_CACHE) int save_mrc_data(void *hob_start); void *find_and_set_fastboot_cache(void); #endif @@ -61,7 +61,7 @@ void printguid(EFI_GUID *guid); #define EFI_HOB_TYPE_HANDOFF 0x0001 #define EFI_HOB_TYPE_MEMORY_POOL 0x0007 -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) +#if CONFIG(ENABLE_MRC_CACHE) #define MRC_DATA_ALIGN 0x1000 #define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) |