drivers/intel/fsp1_0: Drop support

No platform is using this.

Change-Id: I3ea6df4d9ce9043755f319f699adc189d754df1f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

1 files changed, 0 insertions, 136 deletions

diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig
deleted file mode 100644
index 1a1d4f7072..0000000000
--- a/src/drivers/intel/fsp1_0/Kconfig
+++ /dev/null
@@ -1,136 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-config PLATFORM_USES_FSP1_0
-	bool
-	default n
-	select CAR_GLOBAL_MIGRATION
-	select NO_FMAP_CACHE	# doesn't work with CAR_GLOBAL restrictions
-	help
-	  Selected for Intel processors/platform combinations that use the
-	  Intel Firmware Support Package (FSP) 1.0 for initialization.
-
-if PLATFORM_USES_FSP1_0
-
-comment "Intel FSP"
-
-config HAVE_FSP_BIN
-	bool "Use Intel Firmware Support Package"
-	help
-	  Select this option to add an Intel FSP binary to
-	  the resulting coreboot image.
-
-	  Note: Without this binary, coreboot builds relying on the FSP
-	  will not boot
-
-config DCACHE_RAM_BASE
-	hex
-	default 0xfef00000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x4000
-
-config FSP_HEADER_PATH
-	string "Location of FSP headers"
-	help
-	  The path to headers files that are released with the FSP binary.
-
-config FSP_SRC_PATH
-	string "Additional FSP source file"
-	help
-	  Additional source files that are released with the FSP binary.
-
-if HAVE_FSP_BIN
-
-config FSP_FILE
-	string "Intel FSP binary path and filename"
-	help
-	  The path and filename of the Intel FSP binary for this platform.
-
-endif #HAVE_FSP_BIN
-
-config FSP_LOC
-	hex "Intel FSP Binary location in CBFS"
-	help
-	  The location in CBFS that the FSP is located. This must match the
-	  value that is set in the FSP binary.  If the FSP needs to be moved,
-	  rebase the FSP with Intel's BCT (tool).
-
-config ENABLE_FSP_FAST_BOOT
-	bool "Enable Fast Boot"
-	select ENABLE_MRC_CACHE
-	default n
-	help
-	  Enabling this feature will force the MRC data to be cached in NV
-	  storage to be used for speeding up boot time on future reboots
-	  and/or power cycles.
-
-config ENABLE_MRC_CACHE
-	bool
-	default y if HAVE_ACPI_RESUME
-	default n
-	help
-	  Enabling this feature will cause MRC data to be cached in NV storage.
-	  This can either be used for fast boot, or just because the FSP wants
-	  it to be saved.
-
-config MRC_CACHE_FMAP
-	bool "Use MRC Cache in FMAP"
-	depends on ENABLE_MRC_CACHE
-	select CACHE_MRC_SETTINGS
-	default n
-	help
-	  Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
-	  Your FMAP must contain a region named "RW_MRC_CACHE".
-
-config MRC_CACHE_SIZE
-	hex "Fast Boot Data Cache Size"
-	default 0x10000
-	depends on ENABLE_MRC_CACHE
-	depends on !MRC_CACHE_FMAP
-	help
-	  This is the amount of space in NV storage that is reserved for the
-	  fast boot data cache storage.
-
-	  WARNING: Because this area will be erased and re-written, the size
-	  should be a full sector of the flash ROM chip and nothing else should
-	  be included in CBFS in any sector that the fast boot cache data is in.
-
-config VIRTUAL_ROM_SIZE
-	hex "Virtual ROM Size"
-	default ROM_SIZE
-	depends on ENABLE_MRC_CACHE
-	help
-	  This is used to calculate the offset of the MRC data cache in NV
-	  Storage for fast boot.  If in doubt, leave this set to the default
-	  which sets the virtual size equal to the ROM size.
-
-	  Example: Cougar Canyon 2 has two 8 MB SPI ROMs.  When the SPI ROMs are
-	  loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB.  When
-	  the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
-	  size is 16 MB.
-
-config USE_GENERIC_FSP_CAR_INC
-	bool
-	default n
-	help
-	  The chipset can select this to use a generic cache_as_ram.inc file
-	  that should be good for all FSP based platforms.
-
-config FSP_USES_UPD
-	bool
-	default n
-	help
-	  If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
-endif #PLATFORM_USES_FSP1_0