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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-02-16 17:22:37 +0530
committerMartin Roth <martinroth@google.com>2017-05-01 16:26:26 +0200
commit89331cd4c877397adf6b35002d864ac105dfc827 (patch)
treebcef0ac94cb98df6a3ff127dd2fa2cdcfda2e6f5 /src/drivers/ics/954309
parent281ccca373c3b7c96452f35815fcf11274678117 (diff)
soc/intel/common/block: Add Intel common FAST_SPI code
Create Intel Common FAST_SPI Controller code. This code contains the code for SPI initialization which has the following programming - * Get BIOS Rom Region Size * Enable SPIBAR * Disable the BIOS write protect so write commands are allowed * Enable SPI Prefetching and Caching. * SPI Controller register offsets in the common header fast_spi.h * Implement FAST_SPI read, write, erase APIs. Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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