diff options
| author | Rob Barnes <robbarnes@google.com> | 2022-02-11 07:59:21 -0700 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-02-23 16:26:03 +0000 |
| commit | 22372f4ac90780407533ebefc25d1740fc72ce7c (patch) | |
| tree | 786b65fa6ae65ae3e890d9fbe3ba05a4d324aee9 /src/drivers/i2c/tpm | |
| parent | d239aaf741372594fd31e452300816aeaae09000 (diff) | |
cr50: Increase cr50 i2c probe timeout
Turns out 200ms still isn't enough in the worst reset conditions.
There's been some reports of failures at 200ms with some older
cr50 versions. Let's not take any chances and bump this way up
since if this fails, it prevents boot.
BUG=b:213828947
BRANCH=None
TEST=Reboot and suspend_stress on Nipperkin
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5be0a80c064546fd277f66135abc9d0572df11cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/drivers/i2c/tpm')
| -rw-r--r-- | src/drivers/i2c/tpm/cr50.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index 6c12ee4e9e..415285297d 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -441,13 +441,14 @@ static int cr50_i2c_probe(struct tpm_chip *chip, uint32_t *did_vid) int retries; /* - * 200 ms should be enough to synchronize with the TPM even under the + * 1s should be enough to synchronize with the TPM even under the * worst nested reset request conditions. In vast majority of cases - * there would be no wait at all. + * there would be no wait at all. If this probe fails, boot likely + * cannot proceed, so an extra long timeout is appropriate. */ printk(BIOS_INFO, "Probing TPM I2C: "); - for (retries = 20; retries > 0; retries--) { + for (retries = 100; retries > 0; retries--) { int rc; rc = cr50_i2c_read(TPM_DID_VID(0), (uint8_t *)did_vid, 4); |