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authorShaunak Saha <shaunak.saha@intel.com>2017-10-04 23:08:40 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-26 15:55:37 +0000
commit95b61752dbb56b9a7a2da439c5d21e30643661ef (patch)
treeb7856619ddeb70752c935f727a46f9779f8dae0d /src/drivers/i2c/generic
parent66b5acc54bf75b186efea431dfac6eebce527403 (diff)
soc/intel/cannonlake: Add support for C state and P state
This patch adds the C state and P state configurations for cannonlake soc. TEST = Boot and test the CPU states for all the cores are present in "powertop" tool output. Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/21891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/i2c/generic')
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