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authorMatt DeVillier <matt.devillier@gmail.com>2024-07-09 16:54:51 -0500
committerFelix Held <felix-coreboot@felixheld.de>2024-07-11 00:13:42 +0000
commitc4f735105bb4d81eb8a8365bf7ac480676f47608 (patch)
treee22fbbc5308baa5f2af268757ad34d8f2ecd0c60 /src/drivers/i2c/cs42l42
parentbaec1c858d425d7acfa321f4d20f22903e018364 (diff)
soc/amd/phoenix: Fix APOB NV size/base for non-vboot builds
The APOB NV size/base are embedded into the amdfw binary and read by the PSP. These need to be synchronized with the FMAP region used by coreboot to store the APOB data. soc_update_apob_cache() will only use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the NV base passed to the PSP needs to reflect that as well. This fixes the issue of RAM training running on every boot on non-vboot builds for Myst boards. TEST=untested, but same change as made for Mendocino Change-Id: Ib4a78a39badf0a067e22eebe5869e5ea51723f35 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/drivers/i2c/cs42l42')
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