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authorJan Samek <jan.samek@siemens.com>2023-10-16 10:36:58 +0200
committerFelix Held <felix-coreboot@felixheld.de>2024-01-27 14:20:01 +0000
commit545c532902a8a11a7c79d220f353a2da544d00f0 (patch)
tree5b8b0badd6245fa3db64c5fc198364f3876e1f0b /src/drivers/gfx/generic/Kconfig
parent0458a4428d2f7acc44a73f5cf417fa0e0e7d669b (diff)
mb/siemens/mc_ehl3: Use PSE GbE 0 instead of PSE GbE 1
As a result of hardware changes on this board, the PHY previously routed to the PSE GbE 1 is now routed to PSE GbE 0 on the Elkhart Lake SoC. This patch changes the device PCI ID in the board's devicetree and accordingly, the GPIO configuration. BUG=none TEST=Boot into Linux and observe whether both PSE GbE 0 and PCH GbE are working, while PSE GbE 1 remains inactive (not listed by 'ip link') . Change-Id: I322371f944d15134e6f48ecd84a4026c2fced27b Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Diffstat (limited to 'src/drivers/gfx/generic/Kconfig')
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