diff options
| author | Ben Chuang <benchuanggli@gmail.com> | 2021-09-14 11:31:42 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-24 17:56:09 +0000 |
| commit | 325f431a9176cd9726474a08d9942819f4643ed9 (patch) | |
| tree | e7ce5af5e3ba36f72ec2acc59948d28d97c9d358 /src/drivers/genesyslogic/gl9755/gl9755.c | |
| parent | 333652c5b2dd3291a73f922e0b86c3ab9612f4b1 (diff) | |
drivers/genesyslogic/gl9755: Disable ASPM L0s support
When the entry delay of L0s is less than the entry delay of L1, GL9755
will enter L0s state first. When it exits from L0s state, the time of L1
entry will be reset. Therefore, the conditions for entering L1 state
cannot be met. In order to enter L1 state, L0s needs to be disabled.
BUG=b:195611000
TEST=Verify GL9755 enters L1 by observing CLKREQ# de-asserts.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: If121b5cb534eb32bac8992683c3f0eee8946acec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/drivers/genesyslogic/gl9755/gl9755.c')
| -rw-r--r-- | src/drivers/genesyslogic/gl9755/gl9755.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/drivers/genesyslogic/gl9755/gl9755.c b/src/drivers/genesyslogic/gl9755/gl9755.c index a5778e3924..44342c6632 100644 --- a/src/drivers/genesyslogic/gl9755/gl9755.c +++ b/src/drivers/genesyslogic/gl9755/gl9755.c @@ -28,6 +28,9 @@ static void gl9755_enable(struct device *dev) reg |= CFG2_LAT_L1_64US; pci_write_config32(dev, CFG2, reg); + /* Disable ASPM L0s support */ + pci_and_config32(dev, CFG2, ~CFG2_L0S_SUPPORT); + /* Turn off debug mode to enable SCP/OCP */ pci_and_config32(dev, CFG3, ~SCP_DEBUG); |