diff options
| author | Ben Chuang <benchuanggli@gmail.com> | 2021-11-18 16:33:05 +0800 |
|---|---|---|
| committer | Patrick Georgi <patrick@coreboot.org> | 2021-11-23 09:19:25 +0000 |
| commit | e987845fefe76b1a11071fe9cf10862f18dfac7b (patch) | |
| tree | 4cecdf7d58798abd821087aa72d5bef4d7e116ae /src/drivers/genesyslogic/gl9750/Kconfig | |
| parent | ea6a93f14087a72c84c480e67b54cda8b6766930 (diff) | |
drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750
The device is a PCIe Gen1 to SD 3.0 card reader controller to be
used in the Chromebook. The datasheet name is GL9750S and the revision
is 01.
The patch disables ASPM L0s.
BUG=b:206014046
TEST=Verify GL9750 enters L1 by observing CLKREQ# de-asserts.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/drivers/genesyslogic/gl9750/Kconfig')
| -rw-r--r-- | src/drivers/genesyslogic/gl9750/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/drivers/genesyslogic/gl9750/Kconfig b/src/drivers/genesyslogic/gl9750/Kconfig new file mode 100644 index 0000000000..f3449b0d87 --- /dev/null +++ b/src/drivers/genesyslogic/gl9750/Kconfig @@ -0,0 +1,8 @@ +config DRIVERS_GENESYSLOGIC_GL9750 + bool "Genesys Logic GL9750" + help + GL9750 is a PCI Express Rev. 1.1 compliant card reader controller + which integrates PCI Express PHY, memory card access interface, + regulators (3.3V-to-1.2V) and card power switch. Enabling this driver + will disable L0s support, which will allow the device to enter the + PCIe L1 link state. |