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authorJakub Czapiga <jacz@semihalf.com>2022-02-15 11:50:31 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-03-08 16:06:33 +0000
commitad6157ebdfddc39b95e388487e00cadd2bbf368b (patch)
treebbb85c9b13faf74515387ee8978eefd6d79e6b06 /src/drivers/amd/agesa
parente96ade6981c60af4d6f24471d7f6a440ab7bfd4e (diff)
timestamps: Rename timestamps to make names more consistent
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/drivers/amd/agesa')
-rw-r--r--src/drivers/amd/agesa/eventlog.c22
-rw-r--r--src/drivers/amd/agesa/romstage.c6
2 files changed, 14 insertions, 14 deletions
diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c
index 126a2ee1e1..7154c95155 100644
--- a/src/drivers/amd/agesa/eventlog.c
+++ b/src/drivers/amd/agesa/eventlog.c
@@ -28,69 +28,69 @@ static const struct agesa_mapping entrypoint[] = {
.func = AMD_INIT_RESET,
.name = "AmdInitReset",
.entry_id = TS_AGESA_INIT_RESET_START,
- .exit_id = TS_AGESA_INIT_RESET_DONE,
+ .exit_id = TS_AGESA_INIT_RESET_END,
},
{
.func = AMD_INIT_EARLY,
.name = "AmdInitEarly",
.entry_id = TS_AGESA_INIT_EARLY_START,
- .exit_id = TS_AGESA_INIT_EARLY_DONE,
+ .exit_id = TS_AGESA_INIT_EARLY_END,
},
{
.func = AMD_INIT_POST,
.name = "AmdInitPost",
.entry_id = TS_AGESA_INIT_POST_START,
- .exit_id = TS_AGESA_INIT_POST_DONE,
+ .exit_id = TS_AGESA_INIT_POST_END,
},
{
.func = AMD_INIT_RESUME,
.name = "AmdInitResume",
.entry_id = TS_AGESA_INIT_RESUME_START,
- .exit_id = TS_AGESA_INIT_RESUME_DONE,
+ .exit_id = TS_AGESA_INIT_RESUME_END,
},
{
.func = AMD_INIT_ENV,
.name = "AmdInitEnv",
.entry_id = TS_AGESA_INIT_ENV_START,
- .exit_id = TS_AGESA_INIT_ENV_DONE,
+ .exit_id = TS_AGESA_INIT_ENV_END,
},
{
.func = AMD_INIT_MID,
.name = "AmdInitMid",
.entry_id = TS_AGESA_INIT_MID_START,
- .exit_id = TS_AGESA_INIT_MID_DONE,
+ .exit_id = TS_AGESA_INIT_MID_END,
},
{
.func = AMD_INIT_LATE,
.name = "AmdInitLate",
.entry_id = TS_AGESA_INIT_LATE_START,
- .exit_id = TS_AGESA_INIT_LATE_DONE,
+ .exit_id = TS_AGESA_INIT_LATE_END,
},
{
.func = AMD_S3LATE_RESTORE,
.name = "AmdS3LateRestore",
.entry_id = TS_AGESA_S3_LATE_START,
- .exit_id = TS_AGESA_S3_LATE_DONE,
+ .exit_id = TS_AGESA_S3_LATE_END,
},
#if !defined(AMD_S3_SAVE_REMOVED)
{
.func = AMD_S3_SAVE,
.name = "AmdS3Save",
.entry_id = TS_AGESA_INIT_RTB_START,
- .exit_id = TS_AGESA_INIT_RTB_DONE,
+ .exit_id = TS_AGESA_INIT_RTB_END,
},
#endif
{
.func = AMD_S3FINAL_RESTORE,
.name = "AmdS3FinalRestore",
.entry_id = TS_AGESA_S3_FINAL_START,
- .exit_id = TS_AGESA_S3_FINAL_DONE,
+ .exit_id = TS_AGESA_S3_FINAL_END,
},
{
.func = AMD_INIT_RTB,
.name = "AmdInitRtb",
.entry_id = TS_AGESA_INIT_RTB_START,
- .exit_id = TS_AGESA_INIT_RTB_DONE,
+ .exit_id = TS_AGESA_INIT_RTB_END,
},
};
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index 871054b92c..5968f7379f 100644
--- a/src/drivers/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
@@ -40,7 +40,7 @@ static void romstage_main(void)
fill_sysinfo(cb);
- timestamp_add_now(TS_START_ROMSTAGE);
+ timestamp_add_now(TS_ROMSTAGE_START);
board_BeforeAgesa(cb);
@@ -55,14 +55,14 @@ static void romstage_main(void)
agesa_execute_state(cb, AMD_INIT_EARLY);
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
if (!cb->s3resume)
agesa_execute_state(cb, AMD_INIT_POST);
else
agesa_execute_state(cb, AMD_INIT_RESUME);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
/* Work around AGESA setting all memory as WB on normal
* boot path.