drivers/amd/agesa: Don't save regular boot MTRR to flash

Save the regular boot MTRRs that are restored on the S3 path during
the CPU init in cbmem instead of storing them to the SPI flash.

This was probably done because historically this code run with late
cbmem init (in ramstage).

TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine.

Change-Id: Ia58e7cd1afb785ba0c379ba75ef6090b56cb9dc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44294
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>

1 files changed, 10 insertions, 5 deletions

diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c
index fea9d7cc37..51e8a4d27b 100644
--- a/src/drivers/amd/agesa/s3_mtrr.c
+++ b/src/drivers/amd/agesa/s3_mtrr.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <stdint.h>
+#include <cbmem.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
@@ -42,10 +43,13 @@ static const uint32_t msr_backup[] = {
 	TOP_MEM2,
 };
 
-void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
+void backup_mtrr(void)
 {
 	msr_t syscfg_msr;
-	msr_t *mtrr_save = (msr_t *)mtrr_store;
+	msr_t *mtrr_save = (msr_t *)cbmem_add(CBMEM_ID_AGESA_MTRR,
+					      sizeof(msr_t) * ARRAY_SIZE(msr_backup));
+	if (!mtrr_save)
+		return;
 
 	/* Enable access to AMD RdDram and WrDram extension bits */
 	syscfg_msr = rdmsr(SYSCFG_MSR);
@@ -59,14 +63,15 @@ void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
 	syscfg_msr = rdmsr(SYSCFG_MSR);
 	syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
 	wrmsr(SYSCFG_MSR, syscfg_msr);
-
-	*mtrr_store_size = sizeof(msr_t) * ARRAY_SIZE(msr_backup);
 }
 
 void restore_mtrr(void)
 {
 	msr_t syscfg_msr;
-	msr_t *mtrr_save = (msr_t *)OemS3Saved_MTRR_Storage();
+	msr_t *mtrr_save = (msr_t *)cbmem_find(CBMEM_ID_AGESA_MTRR);
+
+	if (!mtrr_save)
+		return;
 
 	/* Enable access to AMD RdDram and WrDram extension bits */
 	syscfg_msr = rdmsr(SYSCFG_MSR);