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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-14 14:59:31 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-25 08:39:05 +0000 |
| commit | 43f6d9d7160be96460f77993465de1570568c569 (patch) | |
| tree | eb71b49d0c8f482e58ae2e46413d92735a58da84 /src/drivers/amd/agesa/romstage.c | |
| parent | e20d6095aee0c73e758199dfa214366104fc9a85 (diff) | |
AGESA binaryPI: Add AGESA entry timestamps
The call to timestamp_rescale_table() had to be moved
before TS_AGESA_INIT_{POST/RESUME}_DONE to have that
timestamp appear without rescaling.
Change-Id: I71e09d3bc4c8657979d447b90fb6ac7cae959479
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/drivers/amd/agesa/romstage.c')
| -rw-r--r-- | src/drivers/amd/agesa/romstage.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index d5b20b76f9..adf6e0d0e3 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -90,8 +90,6 @@ void *asmlinkage romstage_main(unsigned long bist) else agesa_execute_state(cb, AMD_INIT_RESUME); - /* FIXME: Detect if TSC frequency changed during raminit? */ - timestamp_rescale_table(1, 4); timestamp_add_now(TS_AFTER_INITRAM); /* Work around AGESA setting all memory as WB on normal |