From 43f6d9d7160be96460f77993465de1570568c569 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 14 Mar 2019 14:59:31 +0200 Subject: AGESA binaryPI: Add AGESA entry timestamps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The call to timestamp_rescale_table() had to be moved before TS_AGESA_INIT_{POST/RESUME}_DONE to have that timestamp appear without rescaling. Change-Id: I71e09d3bc4c8657979d447b90fb6ac7cae959479 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31515 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/drivers/amd/agesa/romstage.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/drivers/amd/agesa/romstage.c') diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index d5b20b76f9..adf6e0d0e3 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -90,8 +90,6 @@ void *asmlinkage romstage_main(unsigned long bist) else agesa_execute_state(cb, AMD_INIT_RESUME); - /* FIXME: Detect if TSC frequency changed during raminit? */ - timestamp_rescale_table(1, 4); timestamp_add_now(TS_AFTER_INITRAM); /* Work around AGESA setting all memory as WB on normal -- cgit v1.2.3