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authorFelix Held <felix-coreboot@felixheld.de>2022-03-03 20:54:38 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-03-09 19:01:15 +0000
commit697fa74027402e8eb01c69ee6407599f6cacca75 (patch)
tree6d6d09d51c49b2179b737ad930987408356bdba2 /src/device
parent6f73a202d3df000fb2fd83080e0b148add344485 (diff)
soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER
Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to clarify that this isn't the address the SPI flash gets mapped, but the address of the SPI controller MMIO region. This also aligns the register name with the PPR. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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