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author | Jincheng Li <jincheng.li@intel.com> | 2023-08-01 09:47:48 +0800 |
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committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-03-30 13:39:51 +0000 |
commit | 619535778cf7c6b141f8c13b967995327108a50a (patch) | |
tree | a047aa74fd90c0a20ab32d5d490906a4a58f1cd1 /src/device/pci_early.c | |
parent | ec58bebbd6dd6f4b7535948e55cd9241fac4378f (diff) |
vc/intel/fsp/fsp2_0: Add GNR N-1 FSP headers
GNR N-1 FSP headers are a set of stub headers used to fulfill
build sanity check for GNR SoC and CRB codes before the formal
FSP headers are published. The N-1 headers are forward compatible
with the later formal headers.
Change-Id: I1c8125dd64e5a9619073c2f17aeade1d33607870
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/device/pci_early.c')
0 files changed, 0 insertions, 0 deletions