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| author | Tan, Lean Sheng <lean.sheng.tan@intel.com> | 2021-05-26 06:38:28 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-30 20:15:51 +0000 |
| commit | f156f73c624e4ec1d64e6fb5f4cad2aaefc48576 (patch) | |
| tree | fbe8d420f164682aa4bb82ee45d0591566d46865 /src/device/pci_class.c | |
| parent | 33f8fc698ca07a1fd38342e5d84f873896d6cc48 (diff) | |
soc/intel/elkhartlake: Update FADT table
Update FADT table per relevant PM settings:
Fix PM Timer block access size and disable C2 and C3 states for the CPU.
Further on, set the century byte offset in FADT to point to the common location in CMOS.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I72a57bf8ec61c3eabc4522c2695ae4b16979f188
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54958
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/pci_class.c')
0 files changed, 0 insertions, 0 deletions