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| author | Furquan Shaikh <furquan@google.com> | 2020-08-12 14:54:34 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-08-13 04:02:28 +0000 |
| commit | a396c0a7ee5081ca88acf451fd85ef5efb7bf3e7 (patch) | |
| tree | 3dd5cfb47b02b3f126ce23683a683ac02b787cc4 /src/device/pci_class.c | |
| parent | fd8840880d5eeac2db19d3295d33155c6e2557e0 (diff) | |
mb/google/zork: Update PICASSO_FW_*_POSITION to match new layout
CB:44362 ("mb/google/zork: Reorganize chromeos.fmd to increase WP_RO
to 8MiB") updated the flash layout which moved RW_SECTION_A and
RW_SECTION_B to different addresses than before. PICASSO_FW_A_POSITION
and PICASSO_FW_B_POSITION configs need to be updated accordingly to
retain the same behavior as before i.e. amdfw_a/b are placed at the
start of FW_MAIN_A/B by placing them right after the CBFS header.
This change fixes the value of PICASSO_FW_A_POSITION and
PICASSO_FW_B_POSITION to maintain amdfw at the start of RW-A/B CBFS.
BUG=b:161949925
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I177fb38af6380c36397d2a72d5ec00965087d528
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44425
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/pci_class.c')
0 files changed, 0 insertions, 0 deletions