diff options
| author | Ivy Jian <ivy.jian@quanta.corp-partner.google.com> | 2023-09-25 13:32:35 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-09-26 14:09:01 +0000 |
| commit | 9bb02a8db1d200ad82f041aebf3e3ceef6ec2d74 (patch) | |
| tree | 700ad93c7b85b7e268e5f6187c6d52f9adf7ae74 /src/device/pci_class.c | |
| parent | e608a4f4fd2a615f49c3bdafc2b4781be3efb103 (diff) | |
mb/google/rex/var/rex0: Configure I2C5 timing
Configure I2C5 timing in devicetree to ensure I2C devices
meet timing requirement.
BUG=b:300177424
TEST=Build and check I2C devices timing meet spec.
| | I2C5-Before | I2C5-After |
|-------------|-------------|------------|
| FSMB(KHz) | 445.400 | 343.638 |
| TLOW(us) | 1.543 | 2.068 |
| THIGH(us) | 0.475 | 0.604 |
| THD:STA(us) | 0.603 | 0.711 |
| TSU:STA(us) | 0.612 | 0.611 |
| TSU:STO(us) | 0.605 | 0.611 |
| TBUF(us) | >1.914 | >2.044 |
Change-Id: I3bb678b66d55c6bfaff76e3e5500a2a3bc3a2c61
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78111
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/pci_class.c')
0 files changed, 0 insertions, 0 deletions