diff options
| author | Taniya Das <tdas@codeaurora.org> | 2020-02-28 17:05:49 +0530 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-05-11 23:59:59 +0000 |
| commit | 8ad0c86da28debba1cd65b1d1fc898697220581c (patch) | |
| tree | 69db0bf744b8bbfe5b193a25469a21342376f0b9 /src/device/i2c_bus.c | |
| parent | 593a4c32dfc0d91d04596d9a85ddad36c28117e1 (diff) | |
sc7180: clock: Add support to bump CPU levels
Add support to configure the Silver and L3 PLLs and switch the APSS
GFMUX to use the PLL to speed up the boot cores.
Tested: CPU speed frequency validated for speed bump
Change-Id: Iafd3b618fb72e0e8cc8dd297e4a3e16b83550883
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/device/i2c_bus.c')
0 files changed, 0 insertions, 0 deletions