diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-05-06 05:11:28 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-05-07 10:52:44 +0000 |
| commit | 78ba7a7865ed1f60c7f55bfcced305bc8fbdc9c6 (patch) | |
| tree | 876ce8b879c63c3a121701047d35346388192176 /src/device/dram/ddr4.c | |
| parent | 0f3316bc71aab50dbd8464ee2fb5b680947f2ca5 (diff) | |
device/dram/ddr{3,4}: Rename spd_raw_data for specific DDR
Rename different spd_raw_data[] for DDR3 and DDR4.
This is to solve the conflict when we include both "ddr3.h" and ddr4.h"
for example here: src/device/dram/spd.c.
Otherwise, it won't compile as DDR3 and DDR4 have different
spd_raw_data[] size.
Change-Id: I46597fe82790410fbb53d60e04b7fdffb7b0094a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/device/dram/ddr4.c')
| -rw-r--r-- | src/device/dram/ddr4.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 37bd4e2770..14b5dd3f1a 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -70,7 +70,7 @@ const spd_block spd_blocks[] = { {.type = BLOCK_3, 384, 128, 0} }; -static bool verify_block(const spd_block *block, spd_raw_data spd) +static bool verify_block(const spd_block *block, spd_ddr4_raw_data spd) { uint16_t crc, spd_crc; @@ -136,7 +136,7 @@ uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz) * SPD_STATUS_INVALID -- invalid SPD or not a DDR4 SPD * SPD_STATUS_CRC_ERROR -- checksum mismatch */ -int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd) +int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_ddr4_raw_data spd) { u8 reg8; u8 bus_width, sdram_width; |