diff options
| author | Andrey Petrov <anpetrov@fb.com> | 2019-08-01 14:18:06 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-14 03:35:29 +0000 |
| commit | 3f85edbcc554c4db704ed23bdfb1f384f5e2239e (patch) | |
| tree | c475615f6ac1e05cdab1d0a58a9b8e0b97c10230 /src/device/dram/Makefile.inc | |
| parent | bb9506121f709f452d18d135ed163166f76e44e4 (diff) | |
dram: Add basic DDR4 SPD parsing
Add ability to decode basic fields of DDR4 SPDs and produce SMBIOS table
17. XMP, schemas, extended field parising is totally not yet implemented.
Also, put CRC function used in DDR2, DDR3 and DDR4 ina common file.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: If3befbc55cf37e1018baa432cb2f03743b929211
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/device/dram/Makefile.inc')
| -rw-r--r-- | src/device/dram/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index c982ef49e8..f397a534f2 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1 @@ -romstage-y += ddr3.c ddr2.c +romstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c |