Rename almost all occurences of LinuxBIOS to coreboot.

Due to the automatic nature of this update, I am self-acking. It worked in
abuild.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

17 files changed, 34 insertions, 34 deletions

diff --git a/src/cpu/amd/car/copy_and_run.c b/src/cpu/amd/car/copy_and_run.c
index a97ad309b1..e692853385 100644
--- a/src/cpu/amd/car/copy_and_run.c
+++ b/src/cpu/amd/car/copy_and_run.c
@@ -23,7 +23,7 @@ static void copy_and_run(void)
 	uint8_t *src, *dst; 
         unsigned long ilen, olen;
 
-	print_debug("Copying LinuxBIOS to RAM.\r\n");
+	print_debug("Copying coreboot to RAM.\r\n");
 
 #if !CONFIG_COMPRESS 
 	__asm__ volatile (
@@ -55,7 +55,7 @@ static void copy_and_run(void)
 
 	print_debug_cp_run("linxbios_ram.bin   length = ", olen);
 
-	print_debug("Jumping to LinuxBIOS.\r\n");
+	print_debug("Jumping to coreboot.\r\n");
 
         __asm__ volatile (
                 "xorl %ebp, %ebp\n\t" /* cpu_reset for hardwaremain dummy */
@@ -73,7 +73,7 @@ static void copy_and_run_ap_code_in_car(unsigned ret_addr)
         uint8_t *src, *dst;
         unsigned long ilen, olen;
 
-//        print_debug("Copying LinuxBIOS AP code to CAR.\r\n");
+//        print_debug("Copying coreboot AP code to CAR.\r\n");
 
 #if !CONFIG_COMPRESS
         __asm__ volatile (
@@ -105,7 +105,7 @@ static void copy_and_run_ap_code_in_car(unsigned ret_addr)
 
 //        print_debug_cp_run("linxbios_apc.bin   length = ", olen);
 
-//        print_debug("Jumping to LinuxBIOS AP code in CAR.\r\n");
+//        print_debug("Jumping to coreboot AP code in CAR.\r\n");
 
         __asm__ volatile (
                 "movl %0, %%ebp\n\t" /* cpu_reset for hardwaremain dummy */
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index fc30ee9ab1..0f5f831270 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -21,7 +21,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
         "wrmsr\n\t"
 #endif
 
-        /* disable fixed mtrr from now on, it will be enabled by linuxbios_ram again*/
+        /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
         "movl    $0xC0010010, %ecx\n\t"
 //        "movl    $SYSCFG_MSR, %ecx\n\t"
         "rdmsr\n\t"
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 7074f23c5a..ce8ef19647 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -104,7 +104,7 @@ static void post_cache_as_ram(void)
         // wait for ap memory to trained
 //        wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
 #endif
-        /*copy and execute linuxbios_ram */
+        /*copy and execute coreboot_ram */
         copy_and_run();
         /* We will not return */
 
diff --git a/src/cpu/amd/model_gx2/vsmsetup.c b/src/cpu/amd/model_gx2/vsmsetup.c
index add010b790..8c0adf891a 100644
--- a/src/cpu/amd/model_gx2/vsmsetup.c
+++ b/src/cpu/amd/model_gx2/vsmsetup.c
@@ -10,7 +10,7 @@
 /* what a mess this uncompress thing is. I am not at all happy about how this 
  * was done, but can't fix it yet. RGM
  */
-#warning "Fix the uncompress once linuxbios knows how to do it"
+#warning "Fix the uncompress once coreboot knows how to do it"
 #include "../lib/nrv2b.c"
 
 /* vsmsetup.c derived from vgabios.c. Derived from: */
@@ -71,7 +71,7 @@
  *--------------------------------------------------------------------*/
 
 /* Modified to be a self sufficient plug in so that it can be used 
-   without reliance on other parts of core Linuxbios 
+   without reliance on other parts of core coreboot 
    (C) 2005 Nick.Barker9@btinternet.com
 
   Used initially for epia-m where there are problems getting the bios
@@ -320,10 +320,10 @@ struct realidt {
 // that simplifies a lot of things ...
 // we'll just push all the registers on the stack as longwords, 
 // and pop to protected mode. 
-// second, since this only ever runs as part of linuxbios, 
+// second, since this only ever runs as part of coreboot, 
 // we know all the segment register values -- so we don't save any.
 // keep the handler that calls things small. It can do a call to 
-// more complex code in linuxbios itself. This helps a lot as we don't
+// more complex code in coreboot itself. This helps a lot as we don't
 // have to do address fixup in this little stub, and calls are absolute
 // so the handler is relocatable.
 void handler(void)
diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc
index acd85c5185..a92f474457 100644
--- a/src/cpu/amd/model_lx/cache_as_ram.inc
+++ b/src/cpu/amd/model_lx/cache_as_ram.inc
@@ -17,7 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define	LX_STACK_BASE		DCACHE_RAM_BASE		/* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
+#define	LX_STACK_BASE		DCACHE_RAM_BASE		/* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
 #define	LX_STACK_END		LX_STACK_BASE+(DCACHE_RAM_SIZE-1)
 
 #define	LX_NUM_CACHELINES	0x080	/* there are 128lines per way */
@@ -213,7 +213,7 @@ __main:
 
 	cld				/* clear direction flag */
 
-	/* copy linuxBIOS from it's initial load location to
+	/* copy coreboot from it's initial load location to
 	 * the location it is compiled to run at.
 	 * Normally this is copying from FLASH ROM to RAM.
 	 */
@@ -363,8 +363,8 @@ crt_console_tx_string:
 
 #if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
 .section ".rom.data"
-str_copying_to_ram:  .string "Copying LinuxBIOS to ram.\r\n"
-str_pre_main:        .string "Jumping to LinuxBIOS.\r\n"
+str_copying_to_ram:  .string "Copying coreboot to ram.\r\n"
+str_pre_main:        .string "Jumping to coreboot.\r\n"
 .previous
 
 #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
diff --git a/src/cpu/amd/model_lx/vsmsetup.c b/src/cpu/amd/model_lx/vsmsetup.c
index ec0b047907..baf96c0bbc 100644
--- a/src/cpu/amd/model_lx/vsmsetup.c
+++ b/src/cpu/amd/model_lx/vsmsetup.c
@@ -75,7 +75,7 @@
  *--------------------------------------------------------------------*/
 
 /* Modified to be a self sufficient plug in so that it can be used
-   without reliance on other parts of core Linuxbios
+   without reliance on other parts of core coreboot
    (C) 2005 Nick.Barker9@btinternet.com
 
   Used initially for epia-m where there are problems getting the bios
@@ -341,10 +341,10 @@ struct realidt {
 // that simplifies a lot of things ...
 // we'll just push all the registers on the stack as longwords,
 // and pop to protected mode.
-// second, since this only ever runs as part of linuxbios,
+// second, since this only ever runs as part of coreboot,
 // we know all the segment register values -- so we don't save any.
 // keep the handler that calls things small. It can do a call to
-// more complex code in linuxbios itself. This helps a lot as we don't
+// more complex code in coreboot itself. This helps a lot as we don't
 // have to do address fixup in this little stub, and calls are absolute
 // so the handler is relocatable.
 void handler(void)
diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c
index 95a2cd7414..2ec3f5a47e 100644
--- a/src/cpu/amd/sc520/sc520.c
+++ b/src/cpu/amd/sc520/sc520.c
@@ -157,7 +157,7 @@ static void pci_domain_set_resources(device_t dev)
 			/* these are ENDING addresses, not sizes. 
 			 * if there is memory in this slot, then reg will be > rambits.
 			 * So we just take the max, that gives us total. 
-			 * We take the highest one to cover for once and future linuxbios
+			 * We take the highest one to cover for once and future coreboot
 			 * bugs. We warn about bugs.
 			 */
 			if (reg > rambits)
diff --git a/src/cpu/emulation/qemu-i386/northbridge.c b/src/cpu/emulation/qemu-i386/northbridge.c
index 07c8a9b4aa..505511ac95 100644
--- a/src/cpu/emulation/qemu-i386/northbridge.c
+++ b/src/cpu/emulation/qemu-i386/northbridge.c
@@ -86,7 +86,7 @@ static void pci_domain_set_resources(device_t dev)
 			/* these are ENDING addresses, not sizes. 
 			 * if there is memory in this slot, then reg will be > rambits.
 			 * So we just take the max, that gives us total. 
-			 * We take the highest one to cover for once and future linuxbios
+			 * We take the highest one to cover for once and future coreboot
 			 * bugs. We warn about bugs.
 			 */
 			if (reg > rambits)
diff --git a/src/cpu/ppc/mpc74xx/Config.lb b/src/cpu/ppc/mpc74xx/Config.lb
index 8665fa35c0..ee65e41f3b 100644
--- a/src/cpu/ppc/mpc74xx/Config.lb
+++ b/src/cpu/ppc/mpc74xx/Config.lb
@@ -10,7 +10,7 @@ uses DCACHE_RAM_SIZE
 ## Use cache ram for initial setup
 ##
 default USE_DCACHE_RAM=1
-## Set dcache ram above linuxbios image
+## Set dcache ram above coreboot image
 default DCACHE_RAM_BASE=_RAMBASE+0x100000
 ## Dcache size is 32Kb
 default DCACHE_RAM_SIZE=0x8000
diff --git a/src/cpu/ppc/mpc74xx/mpc74xx.inc b/src/cpu/ppc/mpc74xx/mpc74xx.inc
index aa55df8789..ba2c0018d5 100644
--- a/src/cpu/ppc/mpc74xx/mpc74xx.inc
+++ b/src/cpu/ppc/mpc74xx/mpc74xx.inc
@@ -19,7 +19,7 @@
 
 /*
  * The aim of this code is to bring the machine from power-on to the point 
- * where we can jump to the the main LinuxBIOS entry point hardwaremain()
+ * where we can jump to the the main coreboot entry point hardwaremain()
  * which is written in C.
  *
  * At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
@@ -79,7 +79,7 @@
 	isync
 
 	/*
-	 * Clear segment registers (LinuxBIOS doesn't use these)
+	 * Clear segment registers (coreboot doesn't use these)
 	 */
 	mtsr    0, r0
 	isync
diff --git a/src/cpu/ppc/ppc4xx/Config.lb b/src/cpu/ppc/ppc4xx/Config.lb
index 4bf4638762..f739495325 100644
--- a/src/cpu/ppc/ppc4xx/Config.lb
+++ b/src/cpu/ppc/ppc4xx/Config.lb
@@ -10,7 +10,7 @@ uses DCACHE_RAM_SIZE
 ## PPC4XX always uses cache ram for initial setup
 ##
 default USE_DCACHE_RAM=1
-## Set dcache ram above linuxbios image
+## Set dcache ram above coreboot image
 default DCACHE_RAM_BASE=_RAMBASE+0x100000
 ## Dcache size is 16Kb
 default DCACHE_RAM_SIZE=16384
diff --git a/src/cpu/ppc/ppc7xx/Config.lb b/src/cpu/ppc/ppc7xx/Config.lb
index dc2c025511..d6e64b379b 100644
--- a/src/cpu/ppc/ppc7xx/Config.lb
+++ b/src/cpu/ppc/ppc7xx/Config.lb
@@ -10,7 +10,7 @@ uses DCACHE_RAM_SIZE
 ## PPC7XX always uses cache ram for initial setup
 ##
 default USE_DCACHE_RAM=1
-## Set dcache ram above linuxbios image
+## Set dcache ram above coreboot image
 default DCACHE_RAM_BASE=_RAMBASE+0x100000
 ## Dcache size is 16Kb
 default DCACHE_RAM_SIZE=16384
diff --git a/src/cpu/ppc/ppc7xx/ppc7xx.inc b/src/cpu/ppc/ppc7xx/ppc7xx.inc
index 11b54c4207..bd599f324e 100644
--- a/src/cpu/ppc/ppc7xx/ppc7xx.inc
+++ b/src/cpu/ppc/ppc7xx/ppc7xx.inc
@@ -19,7 +19,7 @@
 
 /*
  * The aim of this code is to bring the machine from power-on to the point 
- * where we can jump to the the main LinuxBIOS entry point hardwaremain()
+ * where we can jump to the the main coreboot entry point hardwaremain()
  * which is written in C.
  *
  * At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
@@ -72,7 +72,7 @@
 	isync
 
 	/*
-	 * Clear segment registers (LinuxBIOS doesn't use these)
+	 * Clear segment registers (coreboot doesn't use these)
 	 */
 	li	r3, 15
 1:	mtsrin  r3, r0
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index 1c18a502fa..2cea40f8a7 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -1,4 +1,4 @@
-/* For starting linuxBIOS in protected mode */
+/* For starting coreboot in protected mode */
 
 #include <arch/rom_segs.h>
 
@@ -8,8 +8,8 @@
 	.align	4
 .globl gdtptr
 
-	/* This is the gdt for ROMCC/ASM part of LinuxBIOS.
-	 * It is different from the gdt in GCC part of LinuxBIOS
+	/* This is the gdt for ROMCC/ASM part of coreboot.
+	 * It is different from the gdt in GCC part of coreboot
 	 * which is defined in c_start.S */
 gdt:
 gdtptr:
diff --git a/src/cpu/x86/car/copy_and_run.c b/src/cpu/x86/car/copy_and_run.c
index 6baf53ec8f..a7ccf9c173 100644
--- a/src/cpu/x86/car/copy_and_run.c
+++ b/src/cpu/x86/car/copy_and_run.c
@@ -15,7 +15,7 @@ static void copy_and_run(unsigned cpu_reset)
 	unsigned long dst_len;
         unsigned long ilen, olen;
 
-	print_debug("Copying LinuxBIOS to RAM.\r\n");
+	print_debug("Copying coreboot to RAM.\r\n");
 
 #if !CONFIG_COMPRESS 
 	__asm__ volatile (
@@ -53,7 +53,7 @@ static void copy_and_run(unsigned cpu_reset)
 #else
 	print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n");
 #endif
-	print_debug("Jumping to LinuxBIOS.\r\n");
+	print_debug("Jumping to coreboot.\r\n");
 
 	if(cpu_reset == 1 ) {
 		__asm__ volatile (
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 1adafc8d18..0bc8bbaf07 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -1,5 +1,5 @@
 /*
-	2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
+	2005.12 yhlu add coreboot_ram cross the vga font buffer handling
 	2005.12 yhlu add _RAMBASE above 1M support for SMP
 */
 
@@ -191,7 +191,7 @@ static int lapic_start_cpu(unsigned long apicid)
 	return 1;
 }
 
-/* Number of cpus that are currently running in linuxbios */
+/* Number of cpus that are currently running in coreboot */
 static atomic_t active_cpus = ATOMIC_INIT(1);
 
 /* start_cpu_lock covers last_cpu_index and secondary_stack.
diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c
index 53db758ce2..2ccee666d8 100644
--- a/src/cpu/x86/pae/pgtbl.c
+++ b/src/cpu/x86/pae/pgtbl.c
@@ -1,5 +1,5 @@
 /*
-	2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
+	2005.12 yhlu add coreboot_ram cross the vga font buffer handling
 */
 
 #include <console/console.h>