diff options
| author | Alexander Couzens <lynxis@fe80.eu> | 2015-02-24 03:07:02 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-13 14:51:37 +0100 |
| commit | ed48dfdc4edd08d4e9641a87839a9904fdd98c13 (patch) | |
| tree | 62cfb904c59a29456749709617768e0bd327b620 /src/cpu | |
| parent | 144a68a4ad5123ee03bd9bf0a8596c339e888fd7 (diff) | |
cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY
BIOS Writer's Guide, rev 1.6.0, June 2012:
This MSR controls whether and FERR message is sent over the system bus
when unmasked x87 exceptions are generated.
This feature is not supported from Sandy Bridge processor onwards.
Change-Id: I19b260ca4b62f57c26989430693b00b9853bc441
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8658
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/model_2065x/model_2065x.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 454f7be662..702eceb3b3 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -35,6 +35,8 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 +#define IA32_FERR_CAPABILITY 0x1f1 +#define FERR_ENABLE (1 << 0) #define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 |