summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-09-07 11:38:56 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2013-09-21 06:20:02 +0200
commite28bd4ade6f716024afdff0bac48028a42a62e71 (patch)
tree518e4b663acf7e9bd7b09646c4a976e85c765173 /src/cpu
parentc8883262cf1375616743ba9d1f259b4fcda20d72 (diff)
timestamps intel: Move timestamp scratchpad to chipset
This retrieves back the value stored with store_initial_timestamp() in the bootblock for southbridge. Change-Id: I377c823706c33ed65af023d20d2e4323edd31199 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3908 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/haswell/romstage.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 0cef888b49..06e3a8516a 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -204,10 +204,7 @@ void romstage_common(const struct romstage_params *params)
tsc_t start_romstage_time;
tsc_t before_dram_time;
tsc_t after_dram_time;
- tsc_t base_time = {
- .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
- .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
- };
+ tsc_t base_time = get_initial_timestamp();
#endif
#if CONFIG_COLLECT_TIMESTAMPS