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authorLean Sheng Tan <lean.sheng.tan@intel.com>2021-05-27 22:48:33 -0700
committerWerner Zeh <werner.zeh@siemens.com>2021-06-04 03:47:51 +0000
commit9420e2847e6e3559a5e50eb10206f436b4a14a4f (patch)
tree80f85e9853ad09fec828c72c8f7c74a48cb3c78c /src/cpu
parente219862795958009909c36e3a9298dc07935549b (diff)
soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs
Further add initial Silicon UPD settings for: - PCIe root ports - USB Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55034 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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