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authorAlexander Goncharov <chat@joursoir.net>2023-02-04 15:20:37 +0400
committerElyes Haouas <ehaouas@noos.fr>2023-02-07 04:37:31 +0000
commit893c3ae892961facc9be8bd300160222e694ab34 (patch)
treeec628a8f9371fe96b783c7bf11dee59d065c0df5 /src/cpu
parentdb4b71ff10b48624a1a0b76e3255bd206ef921d5 (diff)
tree: Drop repeated words
Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/x86/Kconfig4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 7e5817537e..1a7d8c6dd6 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -179,7 +179,7 @@ config X86_INIT_NEED_1_SIPI
bool
default n
help
- This option limits the number of SIPI signals sent during during the
+ This option limits the number of SIPI signals sent during the
common AP setup. Intel documentation specifies an INIT SIPI SIPI
sequence, however this doesn't work on some AMD and Intel platforms.
These newer AMD and Intel platforms don't need the 10ms wait between
@@ -197,7 +197,7 @@ config RESERVE_MTRRS_FOR_OS
default n
help
This option allows a platform to reserve 2 MTRRs for the OS usage.
- The Intel SDM documents that the the first 6 MTRRs are intended for
+ The Intel SDM documents that the first 6 MTRRs are intended for
the system BIOS and the last 2 are to be reserved for OS usage.
However, modern OSes use PAT to control cacheability instead of
using MTRRs.