diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-11 21:56:37 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-15 18:06:27 +0000 |
| commit | 7843bd560e65b0a83e99b42bdd58dd6363656c56 (patch) | |
| tree | 0d411ba99ae94da46d3fccaf09f1208fc812bb6f /src/cpu | |
| parent | c583920a748fb8bd7999142433ad08641b06283d (diff) | |
nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK
There is some overlap between things done in bootblock
and romstage like setting BARs.
Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/socket_LGA775/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/intel/socket_LGA775/Makefile.inc | 7 |
2 files changed, 11 insertions, 0 deletions
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8b227bd7e4..8db932ce58 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -19,6 +19,10 @@ config DCACHE_RAM_SIZE hex default 0x4000 # 16 kB +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + config DCACHE_RAM_BASE hex default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index ceb084c900..a7984a9dfb 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -13,7 +13,14 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep +ifneq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +else +bootblock-y += ../car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../../x86/early_reset.S +endif + postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c |