diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-11 21:51:04 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-11 21:51:04 +0000 |
| commit | 535e3b4baa6edc43fb4f7d9ad77854b9eef4c76b (patch) | |
| tree | 0cf4837e4a6b48d7913a1d2819f313070c30a352 /src/cpu | |
| parent | 97fc40b6b1356102190e8f0e700707497e156f11 (diff) | |
Adapt all uses of CONFIG_XIP_ROM_BASE to use
AUTO_XIP_ROM_BASE (as implemented for tinybootblock) if available.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/amd/mtrr/amd_earlymtrr.c | 7 | ||||
| -rw-r--r-- | src/cpu/via/car/cache_as_ram.inc | 8 | ||||
| -rw-r--r-- | src/cpu/x86/car/cache_as_ram.inc | 8 | ||||
| -rw-r--r-- | src/cpu/x86/mtrr/earlymtrr.c | 7 |
4 files changed, 26 insertions, 4 deletions
diff --git a/src/cpu/amd/mtrr/amd_earlymtrr.c b/src/cpu/amd/mtrr/amd_earlymtrr.c index 8b06b5efb3..e5ececbbf8 100644 --- a/src/cpu/amd/mtrr/amd_earlymtrr.c +++ b/src/cpu/amd/mtrr/amd_earlymtrr.c @@ -42,10 +42,15 @@ static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs) wrmsr(TOP_MEM, msr); #if defined(CONFIG_XIP_ROM_SIZE) +#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE +#else +#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE +#endif /* enable write through caching so we can do execute in place * on the flash rom. */ - set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); + set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); #endif /* Set the default memory type and enable fixed and variable MTRRs diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index f59596d171..605e7f4aed 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -83,7 +83,13 @@ clear_fixed_var_mtrr_out: /* MTRRPhysBase */ movl $0x202, %ecx xorl %edx, %edx - movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax +#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE +#else +#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE +#endif + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr /* MTRRPhysMask */ diff --git a/src/cpu/x86/car/cache_as_ram.inc b/src/cpu/x86/car/cache_as_ram.inc index 5c616c52fa..bfc2ebdb31 100644 --- a/src/cpu/x86/car/cache_as_ram.inc +++ b/src/cpu/x86/car/cache_as_ram.inc @@ -200,12 +200,18 @@ clear_fixed_var_mtrr_out: #endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/ #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) +#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE +#else +#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE +#endif /* enable write base caching so we can do execute in place * on the flash rom. */ movl $0x202, %ecx xorl %edx, %edx - movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr movl $0x203, %ecx diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index ff37521957..3c8d5f5eca 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -100,10 +100,15 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) } #if defined(CONFIG_XIP_ROM_SIZE) +#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK +#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE +#else +#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE +#endif /* enable write through caching so we can do execute in place * on the flash rom. */ - set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); + set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); #endif /* Set the default memory type and enable fixed and variable MTRRs |