diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-05 17:18:11 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-14 12:06:12 +0000 |
| commit | 48bf712d359451c9c754f2713be2268eddb19035 (patch) | |
| tree | fe0e06e83ae935d871dad8d0bd17c60a088b9521 /src/cpu | |
| parent | 25176ef022bdd13864fb23d75066134b62d3abbb (diff) | |
cpu/intel/car/non-evict: Update microcode in CAR setup
On CPU's with a non eviction mode we cache the whole ROM to speed up
finding the microcode updates, remove the caching to fill in the non
eviction mode and then turn on caching the whole ROM again to speed
executing XIP code in flash.
Change-Id: Ib7f36678913e0ba8ef1305bca2c482f375b23eaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30682
Reviewed-on: https://review.coreboot.org/c/30813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/car/non-evict/cache_as_ram.S | 43 |
1 files changed, 36 insertions, 7 deletions
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 4ac6d29232..d2beaa7d5a 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -114,6 +114,17 @@ addrsize_set_high: movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + post_code(0x25) /* Enable MTRR. */ @@ -128,6 +139,30 @@ addrsize_set_high: invd movl %eax, %cr0 +#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: +#endif + /* Disable caching to change MTRR's. */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + /* Clear the mask valid to disable the MTRR */ + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + andl $(~MTRR_PHYS_MASK_VALID), %eax + wrmsr + + /* Enable cache. */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd + movl %eax, %cr0 + /* enable the 'no eviction' mode */ movl $NoEvictMod_MSR, %ecx rdmsr @@ -154,15 +189,9 @@ addrsize_set_high: orl $CR0_CacheDisable, %eax movl %eax, %cr0 - /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRR_PHYS_BASE(1), %ecx - xorl %edx, %edx - movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax - wrmsr - movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + orl $MTRR_PHYS_MASK_VALID, %eax wrmsr post_code(0x28) |