soc/intel/*: Get rid of custom microcode caching

Get rid of custom microcode caching in MPinit and SGX code and
use the caching introduced in intel_microcode_find() instead.

Change-Id: If3ccd4dcff221c88839ffeafa812f4c38cede63f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

3 files changed, 7 insertions, 14 deletions

diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index ff6cbec8dc..fd6a82ac17 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -9,11 +9,10 @@
 #include <device/device.h>
 
 /* Parallel MP initialization support. */
-static const void *microcode_patch;
-
 static void pre_mp_init(void)
 {
-	intel_microcode_load_unlocked(microcode_patch);
+	const void *patch = intel_microcode_find();
+	intel_microcode_load_unlocked(patch);
 
 	/* Setup MTRRs based on physical address size. */
 	x86_setup_mtrrs_with_detect();
@@ -32,7 +31,7 @@ static int get_cpu_count(void)
 
 static void get_microcode_info(const void **microcode, int *parallel)
 {
-	*microcode = microcode_patch;
+	*microcode = intel_microcode_find();
 	*parallel = !intel_ht_supported();
 }
 
@@ -98,8 +97,6 @@ static const struct mp_ops mp_ops = {
 
 void mp_init_cpus(struct bus *cpu_bus)
 {
-	microcode_patch = intel_microcode_find();
-
 	if (mp_init_with_smm(cpu_bus, &mp_ops))
 		printk(BIOS_ERR, "MP initialization failure.\n");
 }
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index 44552f5971..dd2aeef135 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -123,8 +123,6 @@ static void model_2065x_init(struct device *cpu)
 }
 
 /* MP initialization support. */
-static const void *microcode_patch;
-
 static void pre_mp_init(void)
 {
 	/* Setup MTRRs based on physical address size. */
@@ -149,8 +147,7 @@ static int get_cpu_count(void)
 
 static void get_microcode_info(const void **microcode, int *parallel)
 {
-	microcode_patch = intel_microcode_find();
-	*microcode = microcode_patch;
+	*microcode = intel_microcode_find();
 	*parallel = !intel_ht_supported();
 }
 
@@ -160,6 +157,7 @@ static void per_cpu_smm_trigger(void)
 	smm_relocate();
 
 	/* After SMM relocation a 2nd microcode load is required. */
+	const void *microcode_patch = intel_microcode_find();
 	intel_microcode_load_unlocked(microcode_patch);
 }
 
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 31099fd486..ef04d3981f 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -466,8 +466,6 @@ static void model_206ax_init(struct device *cpu)
 }
 
 /* MP initialization support. */
-static const void *microcode_patch;
-
 static void pre_mp_init(void)
 {
 	/* Setup MTRRs based on physical address size. */
@@ -492,8 +490,7 @@ static int get_cpu_count(void)
 
 static void get_microcode_info(const void **microcode, int *parallel)
 {
-	microcode_patch = intel_microcode_find();
-	*microcode = microcode_patch;
+	*microcode = intel_microcode_find();
 	*parallel = !intel_ht_supported();
 }
 
@@ -503,6 +500,7 @@ static void per_cpu_smm_trigger(void)
 	smm_relocate();
 
 	/* After SMM relocation a 2nd microcode load is required. */
+	const void *microcode_patch = intel_microcode_find();
 	intel_microcode_load_unlocked(microcode_patch);
 }