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authorDavid Hendricks <dhendrix@chromium.org>2013-04-12 15:11:05 -0700
committerRonald G. Minnich <rminnich@gmail.com>2013-04-17 23:06:40 +0200
commit1fb11d105b4cc0d424884a08814f65e73d36504a (patch)
tree003151ff5de224099d7d746d8da12b9db8605876 /src/cpu
parent1a0b5e1c0594cb1bfe5094ad0c6eb183c9f3a593 (diff)
armv7/exynos5250: Deprecate sdelay in favor of udelay
This gets rid of the clock-tick based sdelay in favor of udelay(). udelay() is more consistent and easier to work with, and this allows us to carry one less variation of timers (and headers and sources...). Every 1 unit in the sdelay() argument was assumed to cause a delay of 2 clock ticks (@1.7GHz). So the conversion factor is roughly: sdelay(N) = udelay(((N * 2) / 1.7 * 10^9) * 10^6) = udelay((N * 2) / (1.7 * 10^3)) The sdelay() periods used were: sdelay(100) --> udelay(1) sdelay(0x10000) --> udelay(78) (rounded up to udelay(100)) There was one instance of sdelay(10000), which looked like sort of a typo since sdelay(0x10000) was used elsewhere. sdelay(10000) should approximate to about 12us, so we'll stick with that for now and leave a note. Change-Id: I5e7407865ceafa701eea1d613bbe50cf4734f33e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3079 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/armltd/cortex-a9/cache.c1
-rw-r--r--src/cpu/samsung/exynos5250/clock_init.c1
-rw-r--r--src/cpu/samsung/exynos5250/dmc_common.c23
-rw-r--r--src/cpu/samsung/exynos5250/dmc_init_ddr3.c7
4 files changed, 19 insertions, 13 deletions
diff --git a/src/cpu/armltd/cortex-a9/cache.c b/src/cpu/armltd/cortex-a9/cache.c
index 957871dba7..4f440ec4e9 100644
--- a/src/cpu/armltd/cortex-a9/cache.c
+++ b/src/cpu/armltd/cortex-a9/cache.c
@@ -12,7 +12,6 @@
*/
#include <common.h>
-#include <system.h>
#include <armv7.h>
/*
diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c
index c8479deef5..c94cadfbd4 100644
--- a/src/cpu/samsung/exynos5250/clock_init.c
+++ b/src/cpu/samsung/exynos5250/clock_init.c
@@ -25,7 +25,6 @@
#include <delay.h>
#include <stdlib.h>
#include <types.h>
-#include <system.h>
#include <console/console.h>
diff --git a/src/cpu/samsung/exynos5250/dmc_common.c b/src/cpu/samsung/exynos5250/dmc_common.c
index 8c4b583a9e..bcfc9fe2c2 100644
--- a/src/cpu/samsung/exynos5250/dmc_common.c
+++ b/src/cpu/samsung/exynos5250/dmc_common.c
@@ -24,12 +24,11 @@
#include <arch/io.h>
#include <assert.h>
-#include <common.h>
+#include <delay.h>
#include <console/console.h>
#include <cpu/samsung/exynos5250/setup.h>
#include <cpu/samsung/exynos5250/dmc.h>
#include <cpu/samsung/exynos5250/clock_init.h>
-#include <system.h>
#include "clock_init.h"
#include "setup.h"
@@ -75,7 +74,7 @@ int dmc_config_zq(struct mem_timings *mem,
*/
i = ZQ_INIT_TIMEOUT;
while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
- sdelay(100);
+ udelay(1);
i--;
}
if (!i)
@@ -84,7 +83,7 @@ int dmc_config_zq(struct mem_timings *mem,
i = ZQ_INIT_TIMEOUT;
while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
- sdelay(100);
+ udelay(1);
i--;
}
if (!i)
@@ -135,21 +134,27 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
* delays? This one and the next were not there for
* DDR3.
*/
- sdelay(0x10000);
+ udelay(100);
/* Sending EMRS/MRS commands */
for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
writel(mem->direct_cmd_msr[i] | mask,
&dmc->directcmd);
- sdelay(0x10000);
+ udelay(100);
}
if (mem->send_zq_init) {
/* Sending ZQINIT command */
writel(DIRECT_CMD_ZQINIT | mask,
&dmc->directcmd);
-
- sdelay(10000);
+ /*
+ * FIXME: This was originally sdelay(10000)
+ * in the imported u-boot code. That may have
+ * been meant to be sdelay(0x10000) since that
+ * was used elsewhere in this function. Either
+ * way seems to work, though.
+ */
+ udelay(12);
}
}
}
@@ -168,7 +173,7 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
/* PALL (all banks precharge) CMD */
writel(DIRECT_CMD_PALL | mask, &dmc->directcmd);
- sdelay(0x10000);
+ udelay(100);
}
}
}
diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
index 9a4ead0583..5bb8a372ff 100644
--- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
@@ -23,12 +23,12 @@
*/
#include <config.h>
+#include <delay.h>
#include <arch/io.h>
#include <console/console.h>
//#include "clock.h"
/* FIXME(dhendrix): untangle clock/clk ... */
#include <cpu/samsung/exynos5-common/clock.h>
-#include <system.h>
#include "clk.h"
#include "cpu.h"
#include "dmc.h"
@@ -44,6 +44,7 @@ static void reset_phy_ctrl(void)
writel(LPDDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
writel(LPDDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
+#if 0
/*
* For proper memory initialization there should be a minimum delay of
* 500us after the LPDDR3PHY_CTRL_PHY_RESET signal.
@@ -56,6 +57,8 @@ static void reset_phy_ctrl(void)
* TODO(hatim.rv@samsung.com): Implement the delay using timer/counter
*/
sdelay(425000);
+#endif
+ udelay(500);
}
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
@@ -236,7 +239,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
* TODO(waihong): Comment on how long this take to
* timeout
*/
- sdelay(100);
+ udelay(1);
i--;
}
if (!i){