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authorStefan Reinauer <reinauer@chromium.org>2012-04-05 15:59:33 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-04-06 02:15:34 +0200
commit334532eeffac3a26ffbd25bdf4808b87cad2a208 (patch)
treee6cc334b2411f5940116d80a4a906f165a961b08 /src/cpu/x86
parentc00dfbc1c8358c1896e70fe147865dab370a5280 (diff)
Add Sandybridge/Cougar Point support to SMM relocation handler
Previously this part of smmrelocate.S had to be omitted because the CONFIG_ options for those components did not exist yet. Add them back. Change-Id: I6ac94ca804e03062724401a08d1d174adac5e830 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/874 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/x86')
-rw-r--r--src/cpu/x86/smm/smmrelocate.S8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 18d668c9dd..b752531c32 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -35,12 +35,20 @@
#include "../../../southbridge/intel/i82801dx/i82801dx.h"
#elif CONFIG_SOUTHBRIDGE_INTEL_SCH
#include "../../../southbridge/intel/sch/sch.h"
+#elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216
+#include "../../../southbridge/intel/bd82x6x/pch.h"
#else
#error "Southbridge needs SMM handler support."
#endif
#if CONFIG_SMM_TSEG
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
+#else
+#error "Northbridge must define TSEG_BAR."
+#endif
#include <cpu/x86/mtrr.h>
#endif /* CONFIG_SMM_TSEG */