diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-15 16:38:51 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-16 04:12:27 +0100 |
| commit | c5917079eb81b10c58cd3e7bfe6b3925baaf9241 (patch) | |
| tree | e07ef6796762e1289430fa146f311d26c951aa65 /src/cpu/x86/tsc | |
| parent | 8ca9a21a43ccc73b3f289affd2384805ec98eb81 (diff) | |
cpu/x86: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
TEST=Build and run on Galileo Gen2
Change-Id: I56ea28826963403dc0719f40c13782c56dc97feb
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18844
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/x86/tsc')
| -rw-r--r-- | src/cpu/x86/tsc/delay_tsc.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index c8b7ba01dc..b2e20f422d 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -47,7 +47,8 @@ static unsigned long calibrate_tsc_with_pit(void) * (interrupt on terminal count mode), binary count, * load 5 * LATCH count, (LSB and MSB) to begin countdown. */ - outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */ + outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */ + outb(CALIBRATE_INTERVAL & 0xff, 0x42); /* LSB of count */ outb(CALIBRATE_INTERVAL >> 8, 0x42); /* MSB of count */ |