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authorMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-06-08 12:32:58 -0500
committerMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-06-14 16:09:09 +0000
commit74d9dac51e58b45eb6c57bb0f29ae1d01f16743f (patch)
treeab2892c4c555b09a20bc5b59ca2bb8b4fb4c3f8f /src/cpu/x86/smm
parent592700b5a6801c98cd2ca3492b5a1db94797ed5a (diff)
mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM
One specific Hynix LPDDR5x DRAM part requires an ABL workaround to eliminate DRAM-related failures during a FAFT test, but due to the use of generic/common SPDs, there is no way for the ABL to determine the DRAM part # itself. Consequently, we will have coreboot check the DRAM part #, and set/clear a CMOS bit as appropriate, which the ABL will check in order to apply (or not apply) the workaround. The ABL already uses byte 0xD of the extended CMOS ports 72/73 for memory context related toggles, so we will use a spare bit there. BUG=b:270499009, b:281614369, b:286338775 BRANCH=skyrim TEST=run FAFT bios tests on frostflow, markarth, and whiterun without any failures. Change-Id: Ibb6e145f6cdba7270e0a322ef414bf1cb09c5eaa Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75698 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
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