diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2021-03-22 19:59:18 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-15 10:56:13 +0000 |
| commit | 26ab9bfeb53a5d73ff4fdb01c8a15417a2f76876 (patch) | |
| tree | 635f0ce598d308c13cb36845702240d1dcd0b47a /src/cpu/x86/smm/smm_stub.S | |
| parent | 5c9bacca32c4554db0d2f04d371525c20488fac4 (diff) | |
*x86: Support x2apic mode
Implement x2apic mode as existing code only supports apic mode.
Use info from LAPIC_BASE_MSR (LAPIC_BASE_MSR_X2APIC_MODE) to check
if apic mode or x2apic mode and implement x2apic mode according to
x2apic specfication.
Reference:
https://software.intel.com/content/www/us/en/develop/download/intel-64-architecture-x2apic-specification.html
BUG=None
BRANCH=None
TEST=boot to OS and check apic mode
cat /proc/cpuinfo | grep "apicid"
ex) can see apicid bigger than 255
apicid : 256
apicid : 260
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I0bb729b0521fb9dc38b7981014755daeaf9ca817
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51723
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/x86/smm/smm_stub.S')
| -rw-r--r-- | src/cpu/x86/smm/smm_stub.S | 32 |
1 files changed, 24 insertions, 8 deletions
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 7c09e04108..f479d62536 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -11,6 +11,7 @@ #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/lapic_def.h> .code32 .section ".module_parameters", "aw", @progbits @@ -29,7 +30,7 @@ fxsave_area_size: * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ apic_to_cpu_num: -.fill CONFIG_MAX_CPUS,1,0xff +.fill CONFIG_MAX_CPUS,2,0xffff /* allows the STM to bring up SMM in 32-bit mode */ start32_offset: .long smm_trampoline32 - _start @@ -97,16 +98,31 @@ smm_trampoline32: /* The CPU number is calculated by reading the initial APIC id. Since * the OS can maniuplate the APIC id use the non-changing cpuid result - * for APIC id (ebx[31:24]). A table is used to handle a discontiguous + * for APIC id (ax). A table is used to handle a discontiguous * APIC id space. */ - mov $1, %eax - cpuid - bswap %ebx /* Default APIC id in bl. */ - mov $(apic_to_cpu_num), %eax - xor %ecx, %ecx +apic_id: + mov $LAPIC_BASE_MSR, %ecx + rdmsr + andl $LAPIC_BASE_MSR_X2APIC_MODE, %eax + jz xapic + +x2apic: + mov $X2APIC_LAPIC_ID, %ecx + rdmsr + jmp apicid_end + +xapic: + movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi + movl (%esi), %eax + shr $24, %eax + +apicid_end: + + mov $(apic_to_cpu_num), %ebx + xor %ecx, %ecx 1: - cmp (%eax, %ecx, 1), %bl + cmp (%ebx, %ecx, 2), %ax je 1f inc %ecx cmp $CONFIG_MAX_CPUS, %ecx |