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authorStefan Reinauer <reinauer@chromium.org>2012-04-02 13:24:04 -0700
committerPeter Stuge <peter@stuge.se>2012-04-04 04:49:09 +0200
commit3aa067f595115a62afdfc9acc33f08e9c96da850 (patch)
tree1dad56c263c7f84d59440ec32654de76b78d6f2b /src/cpu/x86/smm/smihandler.c
parent6efbebdb58357b8d1aad43f51c91defd452296f6 (diff)
Add support to run SMM handler in TSEG instead of ASEG
Traditionally coreboot's SMM handler runs in ASEG (0xa0000), "behind" the graphics memory. This approach has two issues: - It limits the possible size of the SMM handler (and the number of CPUs supported in a system) - It's not considered a supported path anymore in newer CPUs. Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e Signed-off-by: Duncan Laurie <dlaurie@google.com> Acked-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/842 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/x86/smm/smihandler.c')
-rw-r--r--src/cpu/x86/smm/smihandler.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index a6ab87fd65..bbed0f195e 100644
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -25,10 +25,11 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
+#if !CONFIG_SMM_TSEG /* TSEG handler locks in assembly */
typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
/* SMI multiprocessing semaphore */
-static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED;
+static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED;
static int smi_obtain_lock(void)
{
@@ -56,6 +57,7 @@ void smi_release_lock(void)
: "eax"
);
}
+#endif
#define LAPIC_ID 0xfee00020
static inline __attribute__((always_inline)) unsigned long nodeid(void)
@@ -116,6 +118,7 @@ void smi_handler(u32 smm_revision)
unsigned int node;
smm_state_save_area_t state_save;
+#if !CONFIG_SMM_TSEG
/* Are we ok to execute the handler? */
if (!smi_obtain_lock()) {
/* For security reasons we don't release the other CPUs
@@ -128,6 +131,7 @@ void smi_handler(u32 smm_revision)
}
return;
}
+#endif
smi_backup_pci_address();
@@ -145,6 +149,7 @@ void smi_handler(u32 smm_revision)
(0xa8000 + 0x7e00 - (node * 0x400));
break;
case 0x00030100:
+ case 0x00030101: /* SandyBridge */
state_save.type = EM64T;
state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
(0xa8000 + 0x7d00 - (node * 0x400));
@@ -173,7 +178,9 @@ void smi_handler(u32 smm_revision)
smi_restore_pci_address();
+#if !CONFIG_SMM_TSEG
smi_release_lock();
+#endif
/* De-assert SMI# signal to allow another SMI */
smi_set_eos();