diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2012-06-15 15:34:24 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-24 23:30:00 +0200 |
| commit | b91a0f2b83ac7816dc28cac8d3ae13a7d5576864 (patch) | |
| tree | 02b0647a20ac1ae02970d1e67fee9a1e1b4534e5 /src/cpu/x86/mtrr | |
| parent | 9764d4c690bbe4a54429e47a2094230da5fb88f5 (diff) | |
Rename cache_lbmem() to cache_ramstage()
... and don't require it to specify a cache type.
This function is only used on romcc boards, and should go away
(because all boards should be switched to CAR)
Change-Id: Ic32ca3be1afffc773c72c140e88b338d48a0c8ca
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1288
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/x86/mtrr')
| -rw-r--r-- | src/cpu/x86/mtrr/earlymtrr.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 7a1f51de15..593f0664d7 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -21,11 +21,11 @@ static void set_var_mtrr( } #if !defined(CONFIG_CACHE_AS_RAM) || !CONFIG_CACHE_AS_RAM -static void cache_lbmem(int type) +static void cache_ramstage(void) { - /* Enable caching for 0 - 1MB using variable mtrr */ + /* Enable caching for lower 1MB and ram stage using variable mtrr */ disable_cache(); - set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, type); + set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); } |