diff options
| author | Patrick Georgi <patrick@georgi-clan.de> | 2011-10-31 17:07:52 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-11-01 19:06:23 +0100 |
| commit | 784544b934d67dc85ccfcf33e04ff148045836ad (patch) | |
| tree | 8f120ca06da0b126f09526d8814708b95ea6259f /src/cpu/via | |
| parent | 36c04e8a5c54b100a505650218419e112ccc266e (diff) | |
Remove XIP_ROM_BASE
The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).
Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/via')
| -rw-r--r-- | src/cpu/via/car/cache_as_ram.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index ad2805ea2a..aad23690fd 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -240,7 +240,7 @@ testok: movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax wrmsr - /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */ + /* Cache XIP_ROM area to speedup coreboot code. */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx /* |