diff options
| author | Patrick Georgi <patrick@georgi-clan.de> | 2012-03-31 12:52:21 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-25 16:27:07 +0200 |
| commit | 05e740fc40e409dcf8d592f4bbeaf87dc92140c5 (patch) | |
| tree | 5b05e1ea6cd2a9c82ac218984e8ee5526c9b77c5 /src/cpu/via | |
| parent | 8919729307028746cf7bc527ca511183fe3b401b (diff) | |
Replace cache control magic numbers with symbols
Instead of opaque numbers like (1<<29), use
symbols like CR0_NoWriteThrough.
Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/833
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/via')
| -rw-r--r-- | src/cpu/via/car/cache_as_ram.inc | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 90e6d2b88f..bfad5285dd 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -27,6 +27,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <console/post_codes.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE @@ -39,7 +40,7 @@ CacheAsRam: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 invd @@ -139,7 +140,7 @@ clear_fixed_var_mtrr_out: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -219,7 +220,7 @@ testok: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 /* Set the default memory type and enable variable MTRRs. */ @@ -259,7 +260,7 @@ testok: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 invd |