exynos5420: set L2ACTLR parameters for A15 cores

This patch does the following for the A15 cores:
- Disable clean/evict push to external
- Enable hazard detect timout
- Prevent gating the L2 logic clock

This is ported from https://gerrit.chromium.org/gerrit/#/c/60154

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I7ac9f40acecfa7daee6fb81772676bf5119d0536
Reviewed-on: https://gerrit.chromium.org/gerrit/64862
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4441
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

1 files changed, 16 insertions, 0 deletions

diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c
index 1940b88886..bda46de63d 100644
--- a/src/cpu/samsung/exynos5420/cpu.c
+++ b/src/cpu/samsung/exynos5420/cpu.c
@@ -198,4 +198,20 @@ void exynos5420_config_l2_cache(void)
 	 */
 	val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2);
 	write_l2ctlr(val);
+
+	val = read_l2actlr();
+
+	/* L2ACTLR[3]: Disable clean/evict push to external */
+	val |= (1 << 3);
+
+	/* L2ACTLR[7]: Enable hazard detect timeout for A15 */
+	val |= (1 << 7);
+
+	/* L2ACTLR[27]: Prevents stopping the L2 logic clock */
+	val |= (1 << 27);
+
+	write_l2actlr(val);
+
+	/* Read the l2 control register to force things to take effect? */
+	val = read_l2ctlr();
 }