diff options
author | Gabe Black <gabeblack@google.com> | 2013-07-31 22:48:20 -0700 |
---|---|---|
committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 10:48:53 +0100 |
commit | 713853a9c8fca493567548fe3cf0b8107b7fc138 (patch) | |
tree | d6fec9184dd2e2f86924bf77721224020247b216 /src/cpu/samsung/exynos5420/clock.c | |
parent | 9b764a0dcc67a7bbf6e74b35cdd9e3e7c6d59c83 (diff) |
exynos5420: Get rid of the PWM code like on the 5250
The timer code was supposed to be using the mct, and also using the monotonic
timer infrastructure instead of the get_timer function. This change had been
made for the 5250 but not yet for the 5420.
Change-Id: I03a4fbb434f2346761f28fb6bd2218b526f2a4a2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64159
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4418
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/cpu/samsung/exynos5420/clock.c')
-rw-r--r-- | src/cpu/samsung/exynos5420/clock.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index 694f024ca8..b75540e099 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -19,9 +19,9 @@ #include <console/console.h> #include <stdlib.h> +#include <timer.h> #include <assert.h> #include <arch/io.h> -#include "timer.h" #include "clk.h" #include "cpu.h" #include "periph.h" @@ -522,7 +522,7 @@ int clock_epll_set_rate(unsigned long rate) unsigned int epll_con, epll_con_k; unsigned int i; unsigned int lockcnt; - unsigned int start; + struct mono_time current, end; struct exynos5420_clock *clk = samsung_get_base_clock(); epll_con = readl(&clk->epll_con0); @@ -557,14 +557,17 @@ int clock_epll_set_rate(unsigned long rate) writel(epll_con, &clk->epll_con0); writel(epll_con_k, &clk->epll_con1); - start = get_timer(0); + timer_monotonic_get(¤t); + end = current; + mono_time_add_msecs(&end, TIMEOUT_EPLL_LOCK); - while (!(readl(&clk->epll_con0) & + while (!(readl(&clk->epll_con0) & (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) { - if (get_timer(start) > TIMEOUT_EPLL_LOCK) { + if (mono_time_after(¤t, &end)) { printk(BIOS_DEBUG, "%s: Timeout waiting for EPLL lock\n", __func__); return -1; } + timer_monotonic_get(¤t); } return 0; |