exynos5420: re-factor clock_get_periph_rate()

This re-factors clock_get_periph_rate() to be a simpler and also
make a few corrections along the way. To summarize:

- clk_bit_info is no longer used. It had numerous errors and was
  really painful anyway since it was just a bunch of opaque magic
  numbers that made bugs non-obvious.

- Clock source bitfields for peripherals handled in the switch
  statement are 3 bits, not 4. Some divider values are 3 bits,
  some are 4. The earlier code always assumed 4 bits for both
  which included reserved bits in many cases.

- UART source clock and divider shift values were wrong.

- PWM clock divider was being read from the wrong register.

- SPI3 divider value was being read from the wrong register.

- There was a really confusing calculation for SDMMC0 and SDMMC2
  clock rates, but it was never actually used since the switch
  statement never handled PERIPH_ID_SDMMC{0,2} and would thus
  return if they were ever passed into this function.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I0a03a64d8b42fbe83dbf377292597ce681b22f4b
Reviewed-on: https://gerrit.chromium.org/gerrit/65284
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4463
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

1 files changed, 0 insertions, 10 deletions

diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h
index c5e7f589ba..3f97319076 100644
--- a/src/cpu/samsung/exynos5420/clk.h
+++ b/src/cpu/samsung/exynos5420/clk.h
@@ -38,16 +38,6 @@ enum periph_id;
 #define DPLL	9
 #define IPLL	10
 
-/* *
- * This structure is to store the src bit, div bit and prediv bit
- * positions of the peripheral clocks of the src and div registers
- */
-struct clk_bit_info {
-	s8 src_bit;    /* offset in register to clock source field */
-	s8 div_bit;
-	s8 prediv_bit;
-};
-
 unsigned long get_pll_clk(int pllreg);
 unsigned long get_arm_clk(void);
 unsigned long get_pwm_clk(void);