Add .h files for samsung exynos 5250

Per a conversation with Stefan, these chip-dependent files are moved
to the src tree, in the manner of other chips (north and southbridge).

Change-Id: I12645ba05eb241eda200ed06cb633541a6a98119
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Reviewed-on: http://review.coreboot.org/1925
Tested-by: build bot (Jenkins)

1 files changed, 134 insertions, 0 deletions

diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h
new file mode 100644
index 0000000000..f6d7c654d7
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/cpu.h
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _EXYNOS5250_CPU_H
+#define _EXYNOS5250_CPU_H
+
+#include <cpu/samsung/exynos-common/cpu.h>
+
+/* EXYNOS5 */
+#define EXYNOS5_GPIO_PART6_BASE		0x03860000	/* Z<6:0> */
+#define EXYNOS5_PRO_ID			0x10000000
+#define EXYNOS5_CLOCK_BASE		0x10010000
+#define EXYNOS5_POWER_BASE		0x10040000
+#define EXYNOS5_SWRESET			0x10040400
+#define EXYNOS5_SYSREG_BASE		0x10050000
+#define EXYNOS5_TZPC1_DECPROT1SET	0x10110810
+#define EXYNOS5_MULTI_CORE_TIMER_BASE	0x101C0000
+#define EXYNOS5_WATCHDOG_BASE		0x101D0000
+#define EXYNOS5_ACE_SFR_BASE            0x10830000
+#define EXYNOS5_DMC_PHY0_BASE		0x10C00000
+#define EXYNOS5_DMC_PHY1_BASE		0x10C10000
+#define EXYNOS5_GPIO_PART4_BASE		0x10D10000	/* V00..V37 */
+#define EXYNOS5_GPIO_PART5_BASE		0x10D100C0	/* V40..V47 */
+#define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
+#define EXYNOS5_GPIO_PART1_BASE		0x11400000	/* A00..Y67 */
+#define EXYNOS5_GPIO_PART2_BASE		0x11400c00	/* X00..X37 */
+#define EXYNOS5_USB_HOST_EHCI_BASE	0x12110000
+#define EXYNOS5_USBPHY_BASE		0x12130000
+#define EXYNOS5_USBOTG_BASE		0x12140000
+
+#ifndef CONFIG_OF_CONTROL
+#define EXYNOS5_MMC_BASE		0x12200000
+#define EXYNOS5_MSHC_BASE		0x12240000
+#endif
+
+#define EXYNOS5_SROMC_BASE		0x12250000
+#define EXYNOS5_UART_BASE		0x12C00000
+
+#define EXYNOS5_SPI1_BASE		0x12D30000
+#ifndef CONFIG_OF_CONTROL
+#define EXYNOS5_I2C_BASE		0x12C60000
+#define EXYNOS5_SPI_BASE		0x12D20000
+#define EXYNOS5_PWMTIMER_BASE		0x12DD0000
+#define EXYNOS5_SPI_ISP_BASE		0x131A0000
+#endif
+#define EXYNOS5_I2S_BASE		0x12D60000
+#define EXYNOS5_GPIO_PART3_BASE		0x13400000	/* E00..H17 */
+#define EXYNOS5_FIMD_BASE		0x14400000
+#define EXYNOS5_DISP1_CTRL_BASE		0x14420000
+#define EXYNOS5_MIPI_DSI1_BASE		0x14500000
+
+#define EXYNOS5_ADC_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS5_MODEM_BASE		DEVICE_NOT_AVAILABLE
+
+/* Compatibility defines */
+#define EXYNOS_POWER_BASE		EXYNOS5_POWER_BASE
+
+/* Marker values stored at the bottom of IRAM stack by SPL */
+#define EXYNOS5_SPL_MARKER	0xb004f1a9	/* hexspeak word: bootflag */
+
+/* Distance between each Trust Zone PC register set */
+#define TZPC_BASE_OFFSET		0x10000
+
+#ifndef __ASSEMBLY__
+
+#define SAMSUNG_BASE(device, base)				\
+static inline unsigned int samsung_get_base_##device(void)	\
+{								\
+	return cpu_is_exynos5() ? EXYNOS5_##base : 0;		\
+}
+
+SAMSUNG_BASE(adc, ADC_BASE)
+SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
+SAMSUNG_BASE(dsim, MIPI_DSI1_BASE)
+SAMSUNG_BASE(disp_ctrl, DISP1_CTRL_BASE)
+SAMSUNG_BASE(fimd, FIMD_BASE)
+SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
+SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
+SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
+SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
+SAMSUNG_BASE(gpio_part5, GPIO_PART5_BASE)
+SAMSUNG_BASE(gpio_part6, GPIO_PART6_BASE)
+SAMSUNG_BASE(pro_id, PRO_ID)
+
+#ifndef CONFIG_OF_CONTROL
+SAMSUNG_BASE(mmc, MMC_BASE)
+SAMSUNG_BASE(mshci, MSHC_BASE)
+#endif
+
+SAMSUNG_BASE(modem, MODEM_BASE)
+SAMSUNG_BASE(sromc, SROMC_BASE)
+SAMSUNG_BASE(swreset, SWRESET)
+SAMSUNG_BASE(sysreg, SYSREG_BASE)
+SAMSUNG_BASE(timer, PWMTIMER_BASE)
+SAMSUNG_BASE(uart, UART_BASE)
+SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb_otg, USBOTG_BASE)
+SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
+SAMSUNG_BASE(power, POWER_BASE)
+SAMSUNG_BASE(i2s, I2S_BASE)
+SAMSUNG_BASE(spi1, SPI1_BASE)
+#ifndef CONFIG_OF_CONTROL
+SAMSUNG_BASE(i2c, I2C_BASE)
+SAMSUNG_BASE(spi, SPI_BASE)
+SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
+#endif
+#endif
+
+#define EXYNOS5_SPI_NUM_CONTROLLERS	5
+#define EXYNOS_I2C_MAX_CONTROLLERS	8
+
+/* helper function to map mmio address to peripheral id */
+enum periph_id exynos5_get_periph_id(unsigned base_addr);
+
+#endif	/* _EXYNOS5250_CPU_H */