diff options
| author | York Yang <york.yang@intel.com> | 2015-10-14 06:52:32 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-16 17:42:36 +0100 |
| commit | 3ecfdbde14851b408b9f0dd4006c2f733731fedb (patch) | |
| tree | e76669808aba426e23a31922ce93fe9353d3e159 /src/cpu/mips | |
| parent | d35c264b71c923387f93886ec9507bd052b8bedf (diff) | |
intel/fsp1_0: Use dummy microcode when calling FSP TempRamInit
Pass in dummy microcode when calling FSP TempRamInit API. FSP will not
do the microcode load and leave the work to coreboot.
Ensure that BSP has been loaded a microcode before calling TempRamInit
API, otherwise FSP will return error that No Valid Microcode Was Found.
Change has been verified on fsp_baytrail and will be applied to rangeley.
Change-Id: I8247c0503c8eb3d1c8eaa059632fb3a11c9daae9
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/11895
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu/mips')
0 files changed, 0 insertions, 0 deletions