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authorArthur Heymans <arthur@aheymans.xyz>2022-11-01 23:26:07 +0100
committerArthur Heymans <arthur@aheymans.xyz>2022-11-07 13:57:22 +0000
commiteb76a455cd39ec59b7f2ba28baeec9538befd59e (patch)
tree51bd8418d5bf9e130c7ccbc8a9c94a5689d8bbbd /src/cpu/intel
parent6baee3d28729d4b924e8f793c4c7311cebf1f80a (diff)
mb/aopen/dxplplusu: Remove board
This board use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69114 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/Kconfig2
-rw-r--r--src/cpu/intel/Makefile.inc1
-rw-r--r--src/cpu/intel/model_f2x/Kconfig7
-rw-r--r--src/cpu/intel/model_f2x/Makefile.inc6
-rw-r--r--src/cpu/intel/model_f2x/model_f2x_init.c46
-rw-r--r--src/cpu/intel/socket_mPGA604/Kconfig36
-rw-r--r--src/cpu/intel/socket_mPGA604/Makefile.inc9
7 files changed, 0 insertions, 107 deletions
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 43b360bfc4..62f88419bf 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -10,7 +10,6 @@ source "src/cpu/intel/model_1067x/Kconfig"
source "src/cpu/intel/model_106cx/Kconfig"
source "src/cpu/intel/model_206ax/Kconfig"
source "src/cpu/intel/model_2065x/Kconfig"
-source "src/cpu/intel/model_f2x/Kconfig"
source "src/cpu/intel/model_f3x/Kconfig"
source "src/cpu/intel/model_f4x/Kconfig"
source "src/cpu/intel/haswell/Kconfig"
@@ -20,7 +19,6 @@ source "src/cpu/intel/socket_BGA956/Kconfig"
source "src/cpu/intel/socket_FCBGA559/Kconfig"
source "src/cpu/intel/socket_m/Kconfig"
source "src/cpu/intel/socket_p/Kconfig"
-source "src/cpu/intel/socket_mPGA604/Kconfig"
source "src/cpu/intel/socket_441/Kconfig"
source "src/cpu/intel/socket_LGA775/Kconfig"
# Architecture specific features
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 01913de312..92025224d9 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -9,7 +9,6 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956
subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m
subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p
-subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
subdirs-$(CONFIG_CPU_INTEL_MODEL_2065X) += model_2065x
subdirs-$(CONFIG_CPU_INTEL_MODEL_206AX) += model_206ax
subdirs-$(CONFIG_CPU_INTEL_HASWELL) += haswell
diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig
deleted file mode 100644
index eb11a3338d..0000000000
--- a/src/cpu/intel/model_f2x/Kconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-config CPU_INTEL_MODEL_F2X
- bool
- select ARCH_X86
- select SUPPORT_CPU_UCODE_IN_CBFS
- select SMM_ASEG
- select CPU_INTEL_COMMON
- select SSE2
diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc
deleted file mode 100644
index fa1b51ad65..0000000000
--- a/src/cpu/intel/model_f2x/Makefile.inc
+++ /dev/null
@@ -1,6 +0,0 @@
-subdirs-y += ../common
-subdirs-y += ../hyperthreading
-
-ramstage-y += model_f2x_init.c
-
-cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*)
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
deleted file mode 100644
index 294d579f8e..0000000000
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/intel/microcode.h>
-#include <cpu/intel/hyperthreading.h>
-#include <cpu/intel/common/common.h>
-#include <cpu/x86/cache.h>
-
-static void model_f2x_init(struct device *cpu)
-{
- /* Turn on caching if we haven't already */
- enable_cache();
-
- if (!intel_ht_sibling()) {
- /* MTRRs are shared between threads */
- x86_setup_mtrrs();
- x86_mtrr_check();
-
- /* Update the microcode */
- intel_update_microcode_from_cbfs();
- }
-
- /* Start up my CPU siblings */
- intel_sibling_init(cpu);
-};
-
-static struct device_operations cpu_dev_ops = {
- .init = model_f2x_init,
-};
-
-static const struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_INTEL, 0x0f22 },
- { X86_VENDOR_INTEL, 0x0f24 },
- { X86_VENDOR_INTEL, 0x0f25 },
- { X86_VENDOR_INTEL, 0x0f26 },
- { X86_VENDOR_INTEL, 0x0f27 },
- { X86_VENDOR_INTEL, 0x0f29 },
- { 0, 0 },
-};
-
-static const struct cpu_driver driver __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
-};
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
deleted file mode 100644
index 7b086990f7..0000000000
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-config CPU_INTEL_SOCKET_MPGA604
- bool
-
-if CPU_INTEL_SOCKET_MPGA604
-
-config SOCKET_SPECIFIC_OPTIONS
- def_bool y
- select CPU_INTEL_MODEL_F2X
- select MMX
- select SSE
- select UDELAY_TSC
- select TSC_MONOTONIC_TIMER
- select SIPI_VECTOR_IN_ROM
- select CPU_INTEL_COMMON
- select CPU_INTEL_COMMON_TIMEBASE
-
-# mPGA604 are usually Intel Netburst CPUs which should have SSE2
-# but the ramtest.c code on the Dell S1850 seems to choke on
-# enabling it, so disable it for now.
-config SSE2
- bool
- default n
-
-config DCACHE_RAM_BASE
- hex
- default 0xfefc0000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x4000
-
-config DCACHE_BSP_STACK_SIZE
- hex
- default 0x2000
-
-endif # CPU_INTEL_SOCKET_MPGA604
diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc
deleted file mode 100644
index f9dfc67b0c..0000000000
--- a/src/cpu/intel/socket_mPGA604/Makefile.inc
+++ /dev/null
@@ -1,9 +0,0 @@
-subdirs-y += ../model_f2x
-subdirs-y += ../../x86/lapic
-subdirs-y += ../microcode
-
-bootblock-y += ../car/p4-netburst/cache_as_ram.S
-bootblock-y += ../car/bootblock.c
-
-postcar-y += ../car/p4-netburst/exit_car.S
-romstage-y += ../car/romstage.c