summaryrefslogtreecommitdiff
path: root/src/cpu/intel
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2021-07-13 00:54:32 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-07-14 02:24:39 +0000
commit1b46e76df9ef0a4b38d782732ee914ab70667bfa (patch)
tree83b3471f79037cc7376e2817ddd2905922d4f7eb /src/cpu/intel
parente3f7ef22864402e72e1fa6c1df3bc79199c40bdc (diff)
include/cpu/x86/msr: introduce IA32_MC_*(x) macros
When accessing the MCA MSRs, the MCA bank number gets multiplied by 4 and added to the IA32_MC0_* define to get the MSR number. Add a macro that already does this calculation to avoid open coding this repeatedly. Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56243 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel')
-rw-r--r--src/cpu/intel/haswell/haswell_init.c4
-rw-r--r--src/cpu/intel/model_2065x/model_2065x_init.c2
-rw-r--r--src/cpu/intel/model_206ax/model_206ax_init.c2
3 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 9fcb527a16..2d8bd152d7 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -528,14 +528,14 @@ static void configure_mca(void)
/* Enable all error reporting */
msr.lo = msr.hi = ~0;
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_CTL + (i * 4), msr);
+ wrmsr(IA32_MC_CTL(i), msr);
msr.lo = msr.hi = 0;
/* TODO(adurbin): This should only be done on a cold boot. Also, some
* of these banks are core vs package scope. For now every CPU clears
* every bank. */
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
}
/* All CPUs including BSP will run the following function. */
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index dd2aeef135..abf8f610b9 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -81,7 +81,7 @@ static void configure_mca(void)
msr.lo = msr.hi = 0;
/* This should only be done on a cold boot */
for (i = 0; i < 7; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
}
static void model_2065x_init(struct device *cpu)
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 7a40644a6f..bfe1fa57dc 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -309,7 +309,7 @@ static void configure_mca(void)
msr.lo = msr.hi = 0;
/* This should only be done on a cold boot */
for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+ wrmsr(IA32_MC_STATUS(i), msr);
}
static void model_206ax_report(void)