diff options
| author | Brenton Dong <brenton.m.dong@intel.com> | 2016-10-18 11:35:15 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-21 00:10:22 +0100 |
| commit | 0a5971c91bac57970e3f3229b8cda735a17b3a67 (patch) | |
| tree | bf8cf135b317da043224293efe07ec6971fe6010 /src/cpu/intel | |
| parent | f7acdf82cbfaf3e2b2b0db784b822207f1b1d026 (diff) | |
drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support
FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for
Cache-As-Ram initialization and teardown. Add fsp2_0 driver
support for TempRamInit & TempRamExit APIs.
Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.
Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17062
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel')
0 files changed, 0 insertions, 0 deletions