diff options
| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-08-18 14:25:22 -0700 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-10-20 14:32:44 +0000 |
| commit | 052fb7c45136263ed194c24fd4d04488a2608fd3 (patch) | |
| tree | 951b5614c6d21459394a4b6a22d741daa711d6c3 /src/cpu/intel | |
| parent | 621ccf8a975de10a641ba36c9f8065b7fb659611 (diff) | |
x86: Add pre-memory stages CBFS cache scratchpad support
Having a CBFS cache scratchpad offers a generic way to decompress CBFS
files through the cbfs_map() function without having to reserve a
per-file specific memory region.
This commit introduces the x86 `PRERAM_CBFS_CACHE_SIZE' Kconfig to set
the pre-memory stages CBFS cache size. A cache size of zero disables
the CBFS cache feature. The default value is 16 KB which seems a
reasonable minimal value enough to satisfy basic needs such as the
decompression of a small configuration file. This setting can be
adjusted depending on the platform needs and capabilities.
We have set this size to zero for all the platforms without enough
space in Cache-As-RAM to accommodate the default size.
TEST=Decompression of vbt.bin in romstage on rex using cbfs_map()
Change-Id: Iee493f9947fddcc57576f04c3d6a2d58c7368e09
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/slot_1/Kconfig | 3 | ||||
| -rw-r--r-- | src/cpu/intel/socket_441/Kconfig | 3 | ||||
| -rw-r--r-- | src/cpu/intel/socket_BGA956/Kconfig | 3 | ||||
| -rw-r--r-- | src/cpu/intel/socket_FCBGA559/Kconfig | 3 | ||||
| -rw-r--r-- | src/cpu/intel/socket_LGA775/Kconfig | 3 | ||||
| -rw-r--r-- | src/cpu/intel/socket_m/Kconfig | 3 | ||||
| -rw-r--r-- | src/cpu/intel/socket_mPGA604/Kconfig | 3 |
7 files changed, 21 insertions, 0 deletions
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 4ba8747012..fffca39585 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -24,6 +24,9 @@ config DCACHE_RAM_SIZE hex default 0x02000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x1000 diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index 1a549ac328..381b72b3a8 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -13,6 +13,9 @@ config DCACHE_RAM_SIZE hex default 0x8000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x2000 diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 7c42722e82..9197faae9e 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -12,6 +12,9 @@ config DCACHE_RAM_SIZE hex default 0x10000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x2000 diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 223f80d228..95099c58c6 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -15,6 +15,9 @@ config DCACHE_RAM_SIZE hex default 0x8000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x2000 diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 63d6250c62..870fd78ea0 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -12,6 +12,9 @@ config DCACHE_RAM_SIZE hex default 0x8000 # 32 kB +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x2000 diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 2e653e97c1..2e6d432718 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -13,6 +13,9 @@ config DCACHE_RAM_SIZE hex default 0x8000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x2000 diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 8f28670a1d..92a0b43e0f 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -17,6 +17,9 @@ config DCACHE_RAM_SIZE hex default 0x4000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x2000 |