diff options
| author | Christian Walter <christian.walter@9elements.com> | 2019-12-18 15:07:59 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-03-23 16:54:58 +0000 |
| commit | be3979c873d23cb0543e635bba59bd85ab67fed0 (patch) | |
| tree | c8a1064696607573eebd0b03c411a8aa090f015c /src/cpu/intel/speedstep | |
| parent | 09eb8d0c9b3b9e7b765520114d148a19926ff886 (diff) | |
acpi: Change Processor ACPI Name (Intel only)
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.
Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10
FWTS does not return FAIL anymore on ACPI tests
Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/cpu/intel/speedstep')
| -rw-r--r-- | src/cpu/intel/speedstep/acpi.c | 2 | ||||
| -rw-r--r-- | src/cpu/intel/speedstep/acpi/cpu.asl | 16 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 47565f44dc..71570b1e40 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -124,7 +124,7 @@ void generate_cpu_entries(struct device *device) plen = 0; } - /* Generate processor \_PR.CPUx. */ + /* Generate processor \_SB.CPUx. */ acpigen_write_processor( cpuID * cores_per_package + coreID - 1, pcontrol_blk, plen); diff --git a/src/cpu/intel/speedstep/acpi/cpu.asl b/src/cpu/intel/speedstep/acpi/cpu.asl index 9ff3f76727..2d1a47bc78 100644 --- a/src/cpu/intel/speedstep/acpi/cpu.asl +++ b/src/cpu/intel/speedstep/acpi/cpu.asl @@ -12,20 +12,20 @@ */ /* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) -External (\_PR_.CP00, DeviceObj) -External (\_PR_.CP00._PPC) -External (\_PR_.CP01._PPC) +External (\_SB.CNOT, MethodObj) +External (\_SB_.CP00, DeviceObj) +External (\_SB_.CP00._PPC) +External (\_SB_.CP01._PPC) Method (PNOT) { If (MPEN) { - \_PR.CNOT (0x80) // _PPC + \_SB.CNOT (0x80) // _PPC Sleep(100) - \_PR.CNOT (0x81) // _CST + \_SB.CNOT (0x81) // _CST } Else { // UP - Notify (\_PR_.CP00, 0x80) + Notify (\_SB_.CP00, 0x80) Sleep(0x64) - Notify(\_PR_.CP00, 0x81) + Notify(\_SB_.CP00, 0x81) } } |